a metal, plastic, glass, or ceramic casing containing one or more semiconductor electronic components. Individual discrete components are typically etched in silicon wafer before being cut and assembl

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Job Opening at Qualcomm: Signal Integrity Enginee......


Hello,Qualcomm Package Electrical Group has a Job opening in San Diego, CA for a qualified Candidate......

asked by moshiulh

5 years 7 days

0

votes

0

answers
2666 views

Fwd: VRM bode plot transformation into output imp


---------- Forwarded message ----------From: Don Pakbaz Date: Wed, Jan 13, 2016 at 8:43 AMSubject: V......

asked by don.pakbaz

5 years 8 days

0

votes

0

answers
2532 views

VRM bode plot transformation into output imp prof......


Hi,This post is about theories on VRM modelling.For power integrity analysis ideally we should combi......

asked by buenoshun lastest answer by jun.zhou

5 years 8 days

0

votes

13

answers
4746 views

Impact of pad cap on return loss


Hello Experts,I am designing a package for a 12 Gbps Serdes.The package layout is showing a differen......

asked by amit.j.kumar lastest answer by al

5 years 2 months 25 days

0

votes

6

answers
3577 views

Call for Papers - 2016 IEEE 20th Workshop on Sign......


Dear Members,The 2016 IEEE 20th Workshop on Signal and Power Integrity (SPI) will beheld from May 8 ......

asked by dmarc-noreply

5 years 3 months 27 days

0

votes

0

answers
2359 views

What does an unpowered FPGA output look like on a......


Hello SI-list!Trying to figure out if an unpowered, area array FPGA output is connected to PCB using......

asked by jnieznan lastest answer by tom

5 years 4 months 18 days

0

votes

3

answers
3148 views

Re: Necessity of considering Pin Delay for Length......


Hi,Any of your signals set off from your driver's die not pin,usually we measure timing at receiver ......

asked by balaseven

5 years 5 months 8 days

0

votes

0

answers
1962 views

Boards, Chips and Packaging Seminar, October 13


The below one day conference has been organized to deal with the problemsassociated with interacting......

asked by leeritchey

5 years 6 months 26 days

0

votes

0

answers
2165 views

EPEPS Call for Papers - Deadline Extended to July......


Dear Members,The call for papers for the 24th Conference on Electrical Performance of Electronic Pac......

asked by jesa

5 years 7 months 29 days

0

votes

0

answers
1899 views

tight coupling vs EMI


Hello experts,For high frequency signals, it becomes important to widen the traces to reduce inserti......

asked by amit.j.kumar lastest answer by leeritchey

5 years 7 months 22 days

0

votes

4

answers
2952 views

Using Fasthenry for die bumps and package ball in......


Hello All,I am trying to extract inductance of different sections of my package using Fasthenry but ......

asked by amit.j.kumar

5 years 8 months 20 days

0

votes

0

answers
1910 views

Thermal Simulations.- PCB


Hi Experts,I'm newbie to Thermal Simulation.I have some queries listed below, not able to conclude :......

asked by kalyan.krishnan02 lastest answer by cristian.gozzi

5 years 9 months 9 days

0

votes

1

answers
2023 views
5 years 9 months 18 days

0

votes

0

answers
2311 views
5 years 10 months

0

votes

0

answers
2926 views

modeling PDN including die level


I'm used to doing PDN modeling up to the package, or if I can get thepackage layout then including t......

asked by ericsilist lastest answer by dmarc-noreply

5 years 10 months 13 days

0

votes

1

answers
1787 views

S-Parameter model interpretation.


Hi All,  Am running s-parameter model extraction for IC Packages.I have defined the port b/w Die P......

asked by dmarc-noreply lastest answer by goswamisurjendra

5 years 11 months 11 days

0

votes

1

answers
2344 views

Signal Integrity Job opening at Xilinx


Xilinx has a Signal Integrity Sr. Staff Engineer opening immediately in the Package Design Departmen......

asked by ray.anderson

5 years 11 months 15 days

0

votes

0

answers
2455 views

the difference between the pkg/die model in activ......


Hi, experts,During the effort trying to correlate the channel simulation result to the test result, ......

asked by sherman.chen lastest answer by weirsi

5 years 11 months 16 days

0

votes

1

answers
2103 views
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