Job Opening at Qualcomm: Signal Integrity Enginee......

Hello,Qualcomm Package Electrical Group has a Job opening in San Diego, CA for a qualified Candidate......

asked by moshiulh

Fwd: VRM bode plot transformation into output imp

---------- Forwarded message ----------From: Don Pakbaz Date: Wed, Jan 13, 2016 at 8:43 AMSubject: V......

asked by don.pakbaz

VRM bode plot transformation into output imp prof......

Hi,This post is about theories on VRM modelling.For power integrity analysis ideally we should combi......

asked by buenoshun lastest answer by jun.zhou

Impact of pad cap on return loss

Hello Experts,I am designing a package for a 12 Gbps Serdes.The package layout is showing a differen......

asked by amit.j.kumar lastest answer by al

Call for Papers - 2016 IEEE 20th Workshop on Sign......

Dear Members,The 2016 IEEE 20th Workshop on Signal and Power Integrity (SPI) will beheld from May 8 ......

asked by dmarc-noreply

FEXT decreases as frequency increases

asked by dillonhd

What does an unpowered FPGA output look like on a......

Hello SI-list!Trying to figure out if an unpowered, area array FPGA output is connected to PCB using......

asked by jnieznan lastest answer by tom

Re: Necessity of considering Pin Delay for Length......

Hi,Any of your signals set off from your driver's die not pin,usually we measure timing at receiver ......

asked by balaseven

Boards, Chips and Packaging Seminar, October 13

The below one day conference has been organized to deal with the problemsassociated with interacting......

asked by leeritchey

EPEPS Call for Papers - Deadline Extended to July......

Dear Members,The call for papers for the 24th Conference on Electrical Performance of Electronic Pac......

asked by jesa

tight coupling vs EMI

Hello experts,For high frequency signals, it becomes important to widen the traces to reduce inserti......

asked by amit.j.kumar lastest answer by leeritchey

Using Fasthenry for die bumps and package ball in......

Hello All,I am trying to extract inductance of different sections of my package using Fasthenry but ......

asked by amit.j.kumar

Thermal Simulations.- PCB

Hi Experts,I'm newbie to Thermal Simulation.I have some queries listed below, not able to conclude :......

asked by kalyan.krishnan02 lastest answer by cristian.gozzi

Job openings @ Qualcomm

Qualcomm has multiple signal/power integrity engineer openings immediately at San Diego headquarters......

asked by chenchan

Cisco Job Opening - Senior Signal Integrity Engin......

Hi,Can you please post to your site? Applicants can apply at https://jobs.cisco.com/job/San-Jose-Sen......

asked by Steven Goloskov -X (sgolosko - RANDSTAD NORTH AMERICA LP at Cisco)"

Please Post - Cisco Sr. Hardware Engineer

Hi,Can you please post to your site? Applicants can apply at https://jobs.cisco.com/job/San-Jose-Sen......

asked by Steven Goloskov -X (sgolosko - RANDSTAD NORTH AMERICA LP at Cisco)" lastest answer by Steven Goloskov -X (sgolosko - RANDSTAD NORTH AMERICA LP at Cisco)"

modeling PDN including die level

I'm used to doing PDN modeling up to the package, or if I can get thepackage layout then including t......

asked by ericsilist lastest answer by dmarc-noreply

S-Parameter model interpretation.

Hi All,  Am running s-parameter model extraction for IC Packages.I have defined the port b/w Die P......

asked by dmarc-noreply lastest answer by goswamisurjendra

Signal Integrity Job opening at Xilinx

Xilinx has a Signal Integrity Sr. Staff Engineer opening immediately in the Package Design Departmen......

asked by ray.anderson

the difference between the pkg/die model in activ......

Hi, experts,During the effort trying to correlate the channel simulation result to the test result, ......

asked by sherman.chen lastest answer by weirsi