the layered structure of PCB (printed circuit board)
Generic vs. specific stackups for PCB designers
I have a question targeted at the design and signal integrity engineersâ??perspective, not PCB fabri......
asked by jeff.loyer lastest answer by buenoshun
0
votesFollow Up on Transmission Line Tool
Hi,I recently posted a link to a free transmission line calculator I developeda while ago and I got ......
asked by tim
0
votes0
answersFree Transmission Line Calculator
Hi,I've recently returned to consluting work and have the opportunity torelease some tools I develop......
asked by tim lastest answer by michael.huang
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votes4
answersControlled impedance substrate design
Hello All SI expertsi'm designing 2 layer chip substrate ( not board) that should havedifferential 1......
asked by qantrix
0
votes0
answerstune Dk and Df to match simulation and measuremen......
Hi Experts,I have design a SI-test brd and do some measurements by VNA to obtain the Sparameters fro......
asked by zhangjun5960 lastest answer by billh
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votes2
answersPDN resonance mode excited by high speed signal
Hi experts,I'm trying to simulate the phenomena of PDN resonance mode getting excited by the EM fiel......
asked by sherman.chen lastest answer by istvan.novak
0
votes2
answersUncoupled differential signalling
On a recent design I tried out routing loosely coupled differential pairs.Previous tests I've have d......
asked by johan.lans lastest answer by johan.lans
0
votes3
answersSenior SI Engineer Oppertunity
Hello all,Newisys(Sanmina) has an opening for a Senior SI engineer. Please contactMichael if intere......
asked by abbz100
0
votes0
answersWebcast: How to Optimize Your SerDes Design Durin......
Hello,I'm giving a webcast next week entitled "How to Optimize Your SerDes Design During the Pre-lay......
asked by colin_warwick
1
votes0
answersBoard design adjustments by manufacturers
Hello Everyone,After going through a multiple analysis to measurement validation projects, I realize......
0
votes6
answersHas anyone Compiled a Loss-Budget List?
Hi All:I realize that serial-link budgets typically come from component-manufacturer design guides, ......
0
votes1
answersStripline vs. Microstrip selection
Hi All: I have a few 4 inch 25Gbps channel on my board,the design requirementis the lowest tota......
asked by liewluping lastest answer by Gert.Havermann
0
votes4
answersReference for DDR3 signals
Hi Guys,I'm currently doing DDR3 analysis. My board uses DIMM Modules and operates @ 1600Mbps. DIMM ......
asked by razeen_rulez lastest answer by liewluping
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votes3
answersRadiation loss of microstrip
Hi, ExpertsI am investigating radiation loss of microstrip line for high speed digitalcircuit. Read ......
asked by phonondelta lastest answer by telegrapher9
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votes4
answers10L Stackup Selection for Better Impedance Contro......
Hi All: As Donald Telian and Sergio Camerlo's Paper on Designcon 2014 suggest,the pre-preg height ......
asked by liewluping
0
votes0
answersClarification on Trace Routing over Plane Splits
Hi all -I have previously spent time in the high-speed realm, routing PCIe,SATA, HT, and many other ......
0
votes4
answersNordic SI Week May 5-9 with Lee Ritchey
You and your colleagues are all invited to the Nordic SI Week May 5-9 inStockholm. We have three cou......
asked by ro
0
votes0
answersGND vs Power as reference
(I've changed the "Subject" title a bit...)I think that if I was "dead wrong", no one in the entire ......
asked by jeff.loyer lastest answer by shengli.lin.sl
0
votes24
answersFwd: GND vs Power as reference
Jeff Placing a signal on a power layer implies changing reference layers inmost every case, otherwis......
asked by scott
0
votes0
answersCopper width that has DCR within target spec
Hi All,For Power Integrity Analysis, I've calculated target DCR using Maximum Peak current, Voltage ......
asked by praveenkumardr lastest answer by yu.yanfeng
2
answers