A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after manufacturing – hence "field-programmable". The FPGA configuration is genera

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Power Supply Noise injected Jitter impact on SERD......


Hi All,In my design I have high speed interfaces like DDR4 and PCIe 3.0 interfaceoperating at their ......

asked by rameshp3note lastest answer by carsona

4 years 8 months 4 days

0

votes

1

answers
2386 views

differential signal driver\ receiver


Hello,The diffrerantial communication spec:The Lines: H,LVoltage levels: 0-5vLogic:True: H =5v ,L =0......

asked by shimonakrish

4 years 10 months 15 days

0

votes

0

answers
2190 views

Need A Serdes System Engineer


We are looking for a "Serdes System Engineer" for a 12 month contract opportunity in San Jose, CA. K......

asked by rao

4 years 11 months 28 days

0

votes

0

answers
1793 views

What does an unpowered FPGA output look like on a......


Hello SI-list!Trying to figure out if an unpowered, area array FPGA output is connected to PCB using......

asked by jnieznan lastest answer by tom

5 years 16 days

0

votes

3

answers
2955 views

Book advice for PCB design at 30Gbps


HiPlease could someone recommend books or articles that they have found to bewell written and useful......

asked by jonathan.lloyd.riley lastest answer by leeritchey

5 years 1 month 21 days

0

votes

1

answers
1774 views

Skew vs length matching


Hello guys,I am making a board using a FPGA whose serdes runs on 12.5 Gbps.Owing to the FPGA ball ma......

asked by amit.j.kumar lastest answer by jpnathan

5 years 4 months 11 days

0

votes

2

answers
2417 views

HSTL single ended bus to FPGA EVB Connector


Can someone suggest on how to connect HSTL unidirectional signals to HPCconnector of FPGA EVBThe pro......

asked by moshef108

5 years 5 months 9 days

0

votes

0

answers
1751 views

LVDS 2.5V Vcm(common mode) simulation measurement......


Hi experts,I have a board with 100MHz oscillator LVDS 2.5V *AC coupled* with 100nFcapacitors to cloc......

asked by waqaschaudharyciit lastest answer by telegrapher9

5 years 5 months 22 days

0

votes

11

answers
3169 views

IBIS 5.0 model for DDR3 component


Hello experts,In the frame of my research work for my Ph. D. thesis in the field of Power Integrity,......

asked by benoit.goral lastest answer by ferhatyaldiz

5 years 6 months 12 days

0

votes

1

answers
3079 views

Question about jitter at serdes transmitter


We are using an Altera Arria II GX FPGA for a SATA 3 6GBPS interface.I ran some simulations in Hspi......

asked by joel lastest answer by dmarc-noreply

5 years 7 months 10 days

0

votes

4

answers
2813 views

Signal Integrity Job opening at Xilinx


Xilinx has a Signal Integrity Sr. Staff Engineer opening immediately in the Package Design Departmen......

asked by ray.anderson

5 years 7 months 13 days

0

votes

0

answers
2256 views

Termination of unused Ethernet pairs


HiI've got an board with 10/100 Ethernet on it and we have no margin inconducted emissions tests for......

asked by james.dowle lastest answer by leeritchey

6 years 3 months 9 days

0

votes

1

answers
1848 views

Pcie PLL bandwidth


Hello,I am validating chip-chip pcie gen 1 interface.My design has pcie linkbetween CPUASIC and CPUF......

asked by balaseven lastest answer by jpnathan

6 years 3 months 17 days

0

votes

4

answers
2294 views

ODT termination - LPDDR2


Hi,Understanding of ODT in architecture of one LPDDR2 interfaced with FPGA:Please guide me on ODT : ......

asked by mani.kumar lastest answer by paul.taddonio

6 years 4 months 29 days

0

votes

2

answers
2586 views

need advice on DDR3 simulation / termination


I am working on a DDR3 design. It uses an older FPGA (Altera Arria II GX) which does does not suppor......

asked by joel lastest answer by ken

6 years 5 months 3 days

0

votes

14

answers
2135 views

What is the intention of this application of ferr......


Hi,My first post on the reflector! :)I was looking through some documentation for the Xilinx FPGAs a......

asked by carson.au lastest answer by weirsi

6 years 5 months 14 days

0

votes

8

answers
2559 views

"Unconstrained" shapes for better signal integrit......


Hello everyone.Please bear with me until this becomes relevant to signal integrity ;)I've written an......

asked by saardrimer lastest answer by Gert.Havermann

6 years 6 months 16 days

0

votes

1

answers
1619 views

Nordic SI Week May 5-9 with Lee Ritchey


You and your colleagues are all invited to the Nordic SI Week May 5-9 inStockholm. We have three cou......

asked by ro

6 years 8 months

0

votes

0

answers
1721 views

DDR3 is simulation required?


I inherited a DDR3 design done by somebody else.I have never done a DDR design myself but have revie......

asked by joel lastest answer by mgreim001

6 years 8 months 22 days

0

votes

2

answers
1956 views

[Careers at Altera Corporation] Looking for a Boa......


Hi,I am looking for a board designer to join my team. This job opportunity is within San Jose, CA of......

asked by nhramly lastest answer by mgreim001

6 years 11 months 8 days

0

votes

1

answers
1401 views
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