specific to the GNU/Linux operating system. If your question has nothing to do with Linux APIs or Linux-specific behavior you should not use this tag, even if you
Power Supply Noise injected Jitter impact on SERD......
Hi All,In my design I have high speed interfaces like DDR4 and PCIe 3.0 interfaceoperating at their ......
asked by rameshp3note lastest answer by carsona
0
votesDDR4 and PAM4 DesignCon papers
Hi si-listers,I uploaded our DesignCon 2015 technical track papers to:http://signal-integrity.blogs.......
asked by colin_warwick
0
votes0
answersfree Keysight Technologies (formerly Agilent) Sig......
Not too late to register for a free Keysight Technologies seminar on some of the latest simulation t......
asked by heidi_barnes
0
votes0
answerssource of DDR 4 timing recommendations
Can anyone help me understand the source of the pcb routing recommendationsI see for DDR4. For inst......
asked by ericsilist lastest answer by Nitin_Bhagwath
0
votes6
answers8th Signal Integrity Symposium, Penn State Harris......
Subject: 8th Signal Integrity Symposium, Penn State HarrisburgDear Colleagues:We are pleased to invi......
asked by awm2
0
votes0
answersDesignCon 2014 papers from Agilent available for ......
Hi si-listers,We've posted the DesignCon 2014 papers that we authored or co-authored. "Modeling, Ext......
asked by colin_warwick lastest answer by movax
0
votes2
answersDDR4 Simulation in Hyperlynx
Hi All,Could some one clarify me on DDR4 simulation in Hyperlynx 8.2.1 :How the Data Mask for DDR4 ......
asked by shankar.electronics lastest answer by Arpad_Muranyi
0
votes1
answersDDR4 Logic Level
Hi Experts,It seems that input logic level VIH(AC)&VIH(DC)&VIL(DC)&VIL(AC) are not given out in the ......
asked by icermail
0
votes0
answersAnnouncement of On-line Course Event: Mastering t......
Content-Type: multipart/alternative; boundary="----=_NextPart_002_0048_01CEBAEB.269F5460"----......
asked by hanymhfahmy
0
votes0
answersOracle has an opening for a SI Engineer in Burlin......
Hello all, Oracle has an opening for an SI Engineer in Burlington, MA. If interested you can ap......
asked by tom.wenners
0
votes0
answersDDR4 IBIS models
Hi,Does anyone have a source for DDR4 IBIS buffer models? I tried all the big name memory suppliers ......
asked by pcbguy lastest answer by anil.lingambudi
0
votes1
answersDDR3/DDR4 footprint
Hello,I would like to understand can DDR3 part be swapped with DDR4 if it is pincompatible other tha......
asked by bhoumiks
0
votes0
answersDDR 4 Features
Hello,as we have just touched DDR4 ..Some time ago I made a short overview DDR2 vs. DDR3. I did an u......
asked by Hermann.Ruckerbauer
0
votes0
answersAMD Signal Integrity Job Opportunity
Hi Doug, I am wondering if you could help me with a referral. I am looking for asenior level sign......
asked by jworth
0
votes0
answersInterfacing DDR 400 DRAM Chips to Xilinx Virtex I......
Hi Gurus, I need to interface DDR400 DRAM chips andDDR333 SO-DIMM Module to a Virtex II FPGA.......
asked by sivakumar_skm lastest answer by weirsp
1
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