Gen 2 of double data rate synchronous dynamic random-access memory interface.

learn moreā€¦

5 years 10 months 23 days

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votes

0

answers
2600 views

Peak to peak Vref AC noise amplitude


Hi,In DDR2, VREF(t) may temporarily deviate from VREF(DC) by no more than +/-1% VDD.When I referred ......

asked by kbmanick

7 years 3 months 26 days

0

votes

0

answers
1791 views

write time budget for DDR2


HiI am calculating the Data write time budget for DDR2 interface.I referred the following document.h......

asked by kbmanick

7 years 4 months 15 days

0

votes

0

answers
2000 views

Looking for Hyperlynx - Signal Integrity Experts


Thanks to all those that responded to our job offer. We did hire someone, so thanks, but we still ne......

asked by charles

7 years 8 months 15 days

0

votes

0

answers
1692 views

DDR2/3 and tQH/tQHS


We've been having some internal discussions on DDR tQH/tQHS that I'm hoping some (memory) experts ca......

asked by conrad.herse

7 years 10 months 16 days

0

votes

0

answers
1888 views

DDR 4 Features


Hello,as we have just touched DDR4 ..Some time ago I made a short overview DDR2 vs. DDR3. I did an u......

asked by Hermann.Ruckerbauer

8 years 1 month 3 days

0

votes

0

answers
1852 views

SI Lab Lead at Xilinx


My team is looking for a senior SI Lab Lead to drive our SI lab activities. Please contact me at yon......

asked by yong.wang

8 years 2 months 16 days

0

votes

0

answers
1901 views

Infinite subckt recursion error in Sisoft


Hi All,I am trying to simulate one of the nets (dq_2R) in the Sisoft ddr2design kits.But I get "infi......

asked by hithesh

8 years 7 months 26 days

0

votes

0

answers
1272 views

Design of Experiments


Hi,I've been using Design of Experiments methodology for a while now to analyzeinterfaces that can h......

asked by tim.coyle

8 years 9 months 2 days

0

votes

0

answers
1205 views

US Job Opportunity - Senior Application Engineer


Hello,Mentor Graphics currently has an opportunity for a Senior Application Engineer in the Orlando,......

asked by Mark_Deley

8 years 10 months 26 days

0

votes

0

answers
1673 views
9 years 2 months 25 days

0

votes

0

answers
1636 views

A high-speed I/O engineer/specialist job opening ......


Hello:Altera (Nasdaq: ALTR, Altera Corporation designs, manufactures and markets a broad range of h......

asked by mpli

9 years 7 months 6 days

0

votes

0

answers
1782 views

SoC - DDR2 clock jitter vs filler cell count?


Hi,What Cadence workflow do folks use to identify requisite filler-cell counton an SoC, or AC power ......

asked by nemisonic

9 years 8 months 1 day

0

votes

0

answers
1541 views

Voltage levels of DDR2 simulation in Hyperlynx


Sorry if this is a bit basic for this mailing list. I'm trying to simulateDDR2 terminations accordin......

asked by allanw

9 years 9 months 13 days

0

votes

0

answers
1552 views

Plexus Digital Design Job Opportunity


ATTENTION - HARDWARE ENGINEERS! Experience the difference that Plexus has to offer. With over 30 ye......

asked by jeffrey.haug

10 years 4 months 4 days

0

votes

0

answers
1799 views

question on ddrii


Hi SI expert,I am working on a new ddrii design. I have a few questions.1. In my application, the cl......

asked by joewang9527

10 years 9 months 5 days

0

votes

0

answers
1273 views

DDR2 SSTL class I interface


Hi all,In my design, I am using the x8 DDR2 memory interfaced with FPGA.FPGA can only support SSTL C......

asked by vicchemical

10 years 9 months 14 days

0

votes

0

answers
1175 views

Re: [Possible SPAM] DDR2 to Virtex 5 heating up a......


Charlene,You should expect more power dissipation based on the removal of all the series terms and t......

asked by mhumphreys

10 years 10 months 25 days

0

votes

0

answers
1291 views

series switches in DDR2 designs


Hi All, I was wondering why are the ibis series switch devices used in the DDR2designs. Thats the fi......

asked by sivaram

11 years 6 months 2 days

0

votes

0

answers
448 views
11 years 7 months 24 days

0

votes

0

answers
561 views
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