Gen 2 of double data rate synchronous dynamic random-access memory interface.

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Including submodel selection keyword in IBIS mode......


Hi SI users,We have been generating IBIS models for DDR2 memory and have always come across a proble......

asked by Brijesh.Shah lastest answer by Brijesh.Shah

5 years 2 months 14 days

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votes

3

answers
2508 views
5 years 9 months 14 days

0

votes

0

answers
2527 views

SigNoise errors/warnings during simulation


We are trying to simulate a topology.Driver is MPC8349EHere are the Models available for DDR2. ddr2_......

asked by malli.1729 lastest answer by malli.1729

5 years 11 months 17 days

0

votes

2

answers
2072 views

DDR2 problem


Having some issues with a 225MHz DDR2 implementation at high temperature.I am wondering if the probl......

asked by bryan lastest answer by Hermann.Ruckerbauer

5 years 11 months 21 days

0

votes

3

answers
2166 views

Point to point simulation results


Hi,I am trying to simulate a topology.it consists of driver --> 0 ohm resistor --> MS line (length v......

asked by malli.1729 lastest answer by sherman.chen

6 years 2 days

0

votes

3

answers
2174 views

Where SSTL_15 (DDR3 1.5V SSTL standard) is availa......


Hi,I can able to find SSTL25,SSTL18 for corresponding DDR and DDR2.Where can i get SSTL_15 (DDR3 1.5......

asked by malli.1729 lastest answer by Hermann.Ruckerbauer

6 years 1 month 1 day

0

votes

2

answers
3748 views

DDR controller board reference designs


Hi,JEDEC provides number of reference designs for memory boards. But Icouldn't find any controller b......

asked by Si-List lastest answer by wtariq

6 years 4 months 15 days

0

votes

4

answers
1820 views

DDR3-1600 Double-Tee Topology


Hi Everyone,Has anyone tried using a double-tee topology with their address/command/control signals ......

asked by josephaday lastest answer by prashant.jaiswar

6 years 9 months 13 days

0

votes

19

answers
3450 views

Regarding AC Input test conditions and Slew rate ......


When i am reading DDR2 specifications,i got 2 different definitions for input signal slew rate , one......

asked by malli.1729 lastest answer by ferhatyaldiz

6 years 10 months 18 days

0

votes

1

answers
1858 views

cross talk threshold in DDR2


HiHow to calculate the cross talk threshold which has to be considered inDDR2 interface simulation? ......

asked by kbmanick lastest answer by wufengthu

7 years 1 day

0

votes

1

answers
1650 views

15 ohm resistor in DDR3 DIMMs


Hi,Could anyone please specify the reason why DDR3 DIMMs use a 15 ohm resistor right after the conne......

asked by Sumant.Srikant lastest answer by weirsi

7 years 1 month 26 days

0

votes

3

answers
2547 views

Peak to peak Vref AC noise amplitude


Hi,In DDR2, VREF(t) may temporarily deviate from VREF(DC) by no more than +/-1% VDD.When I referred ......

asked by kbmanick

7 years 2 months 17 days

0

votes

0

answers
1722 views

DDR2-Vref Noise


HiIn ddr2, VREF noise causes strobe-to-data skew. Since DQ and DQS areconnected to same Vref, then h......

asked by kbmanick lastest answer by Hermann.Ruckerbauer

7 years 2 months 24 days

0

votes

3

answers
1885 views

DDR2 spacing rule


Hi All,Why data lines of same byte in ddr2 routed together?As we know all the datalines in a DDR2 ru......

asked by balaseven lastest answer by weirsi

7 years 2 months 2 days

0

votes

5

answers
1894 views

write time budget for DDR2


HiI am calculating the Data write time budget for DDR2 interface.I referred the following document.h......

asked by kbmanick

7 years 3 months 6 days

0

votes

0

answers
1942 views

DDR2-Signal level-Clarification needed


Hi,To confirm my understanding, I am in need of the values X1,X2,Y1 and Y2.Waveform is DDR2- DQS sig......

asked by kbmanick lastest answer by Hermann.Ruckerbauer

7 years 3 months 14 days

0

votes

1

answers
1686 views

eye mask- DDR2 address/command


HiI would like to know whether any standard eye mask available for DDR2-address/command signals or n......

asked by kbmanick lastest answer by Hermann.Ruckerbauer

7 years 4 months 5 days

0

votes

1

answers
1786 views

ddr2-ringing and non monotonous conditions


Hi,*In DDr2 simulations, How to reduce ringing and non monotonous conditionswhen we have a point to ......

asked by kbmanick lastest answer by Hermann.Ruckerbauer

7 years 4 months 12 days

0

votes

2

answers
1887 views

stimulus doubt - address simulation for DDR2.


Dear ExpertsI have done the address simulation for DDR2.When I give a stimulus using 200MHz oscillat......

asked by kbmanick lastest answer by weirsi

7 years 4 months 1 day

0

votes

2

answers
1772 views

DDR2 length matching address and clock


Dear Experts,This is regarding the trace length matching between DDR2 address and clocksignals.*As p......

asked by kbmanick lastest answer by weirsi

7 years 5 months 9 days

0

votes

1

answers
1909 views
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