PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe, is a high-speed serial computer expansion bus standard designed to replace the older PCI, PCI-X, and AGP bus st

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IO Buffer technique used in HSD interfaces like P......


*Hi All,*Could you please let me know which IO technique is used at PCIe gen 3.0Data IO buffers, tha......

asked by rameshp3note

4 years 7 months 14 days

0

votes

0

answers
1956 views

Power Supply Noise injected Jitter impact on SERD......


Hi All,In my design I have high speed interfaces like DDR4 and PCIe 3.0 interfaceoperating at their ......

asked by rameshp3note lastest answer by carsona

4 years 8 months 4 days

0

votes

1

answers
2387 views

ground recessing


Hi experts,I approach a case about ground recessing. For eight PCIE lanes, the sixteenAC caps are in......

asked by zhangjun5960 lastest answer by leeritchey

4 years 9 months 25 days

0

votes

16

answers
4034 views

redriver issue


Hi all,I think redriver is an old and still difficult topic.we approach in simulation, redriver can ......

asked by zhangjun5960 lastest answer by zhangjun5960

4 years 9 months 7 days

0

votes

9

answers
4229 views

Exciting Openings for High Speed Applications Eng......


Hello All,We have several openings in Altera - San Jose for High Speed Applications Engineers.Intere......

asked by mdun

4 years 10 months 16 days

0

votes

0

answers
2095 views
5 years 3 days

0

votes

5

answers
1861 views

critical insetion loss at 4GHz for PCIe 3


Hi experts,I have a question that "PCI Express® Base Specification Revision 3.0" hasno illustration......

asked by zhangjun5960 lastest answer by stevenzhaozhenwei

5 years 6 days

0

votes

2

answers
2033 views

RegardingDual Stripline PCB routing


HiI am planning to design a PCB board using Dual Stipline. The board has several high speed interfac......

asked by VIVEK.VISHWANATH lastest answer by scott

5 years 9 days

0

votes

3

answers
2269 views

Do SERDES interfaces need Power Aware SI channel ......


*Hi Team,*Could anybody let me know the importance of Power Aware simulation in todayHigh Speed appl......

asked by rameshp3note lastest answer by chris.cheng

5 years 17 days

0

votes

2

answers
2499 views

Serdes Queries


Hi All,I have some queries w.r.t. Serdes.1. Ideally CDR transfer function -3dB corner freq(Low pass ......

asked by bhavanipadhi lastest answer by bhavanipadhi

5 years 2 months 21 days

0

votes

2

answers
2228 views

[SI-LIST]: PCIE3 Tx Coefficients & Compliance tes......


Hi All,I was doing PCIe3 Tx compliance for Add-in card. I see that there are 11presets P0 to P10 to ......

asked by ah.vinod

5 years 4 months 1 day

0

votes

0

answers
1748 views

[SI-LIST]: PCIe2 Rx Eye Spec inside Pad


Hi All,I was trying to measure BER contour (Eye) inside PCIe2 Rx after CTLE-CDR,not on RX pins.I see......

asked by ah.vinod lastest answer by Joseph.Schachner

5 years 4 months 4 days

0

votes

1

answers
2121 views

pcie base and pcie cem


Hi experts:I am studying the pcie,could anyone tell me what's the difference betweenthe pcie base sp......

asked by hanmoggq lastest answer by wangzhiqian

5 years 5 months 2 days

0

votes

1

answers
2773 views
5 years 6 months 28 days

0

votes

0

answers
2731 views

Why are PCIe card edges beveled and DIMMs aren't?


Does anyone know why they bevel PCIe cards but don't bevel DIMMs? We're guessing that they want les......

asked by jeff.loyer lastest answer by Hermann.Ruckerbauer

5 years 6 months 29 days

0

votes

5

answers
3444 views

Mastering High Speed Serial Tech Class -


Hi everyone, A quick note to let you know that I'm teach classes on high speed serialtech in Penang ......

asked by ransom

5 years 6 months 19 days

0

votes

0

answers
2053 views

S-Parameter model interpretation.


Hi All,  Am running s-parameter model extraction for IC Packages.I have defined the port b/w Die P......

asked by dmarc-noreply lastest answer by goswamisurjendra

5 years 7 months 9 days

0

votes

1

answers
2148 views

PCIe 3.0 Clock Jitter Tool


I am looking for PCIe 3.0 Clock Jitter Compliance measurement  tool. Read about many are using Inte......

asked by dmarc-noreply lastest answer by Joseph.Schachner

5 years 7 months 12 days

0

votes

442

answers
3280 views

Clock Jitter Compliance measurement  tool


Ashish,They (Intel) will not share this tool unless you are engaged, in someway, with the team that'......

asked by sio2man1

5 years 7 months 12 days

0

votes

0

answers
1994 views
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