TDR Rise time

Hi,Can I get help in understanding TDR rise time calculation? I came across10% to 90% calculation an......

asked by gmanikandan20 lastest answer by richard.mellitz

ground recessing

Hi experts,I approach a case about ground recessing. For eight PCIE lanes, the sixteenAC caps are in......

asked by zhangjun5960 lastest answer by leeritchey

Testing DVI Cables

Can someone point me to a company that can test DVI cables?I need to perform a TDR test for the foll......

asked by charles lastest answer by al

Saturday RF course to be held in Santa Clara, CA

The IEEE Microwave Theory and Techniques Society will hold a one day course"RF, EMI/EMC and Gigabit ......

asked by olaney lastest answer by olaney

TDR obtained by fourier transform of S11

asked by zhangjun5960 lastest answer by istvan.novak

What does an unpowered FPGA output look like on a......

Hello SI-list!Trying to figure out if an unpowered, area array FPGA output is connected to PCB using......

asked by jnieznan lastest answer by tom

Why do we still TDR pcbs

  Hi folks,See lots of discussion this month on whether SI has become commoditized. I'll hold off ......

asked by dmarc-noreply lastest answer by al

edge connector layout optimization

I'm designing 6Gbps interconnect using edge connector.i try to optimize it's layout using this flow1......

asked by qantrix

the impedance of via

Hi Dear experts,For the same size of vias (10mils) and antipads (40mils), When it connectsto 100ohm ......

asked by zhangjun5960 lastest answer by shlepnev

TDR & Impedance rise in lossy interconnects

Hello,When running a TDR measurement on a lossy channel such as long backplane Ialways see a positiv......

asked by bbakshan lastest answer by bbakshan

some questions abou a PCB test coupon to measure ......

Hi experts,I have designed a PCB test coupon to measure the impedance curve andcrosstalk curve from ......

asked by zhangjun5960 lastest answer by istvan.novak

Re: some questions about a PCB test coupon to mea......

Ching-Chao As Al Neves pointed out if the DUT is swamped out by ringing from poorly designed launche......

asked by tom lastest answer by cchwang2013

100ohm via model

Hi Experts,I'm designing a 100 ohm via model with 5% tolerance for 15 gbps lane (260mil thick board ......

asked by sureshkumar.ayyavu lastest answer by sureshkumar.ayyavu

Cisco Job Opening - Senior Signal Integrity Engin......

Hi,Can you please post to your site? Applicants can apply at https://jobs.cisco.com/job/San-Jose-Sen......

asked by Steven Goloskov -X (sgolosko - RANDSTAD NORTH AMERICA LP at Cisco)"

Please Post - Cisco Sr. Hardware Engineer

Hi,Can you please post to your site? Applicants can apply at https://jobs.cisco.com/job/San-Jose-Sen......

asked by Steven Goloskov -X (sgolosko - RANDSTAD NORTH AMERICA LP at Cisco)" lastest answer by Steven Goloskov -X (sgolosko - RANDSTAD NORTH AMERICA LP at Cisco)"

SI intern - Cisco Systems SJ

Hi all,Cisco SI team in San Jose has several openings for SI interns starting in May. We are looking......

asked by msapozhn

Time Domain Simulation with Limited Frequency Ran......

Hi All,I am trying to figure out what is the optimal approach to get the most accurate time domain s......

asked by zidaneharoldwang lastest answer by shlepnev

S parameters and TDR characteristics for multipoi......

Hi everyone,Have you done some research about S parameters and TDR characteristics for multipoint st......

asked by junz2 lastest answer by junz2

Signal Integrity Job opening at Xilinx

Xilinx has a Signal Integrity Sr. Staff Engineer opening immediately in the Package Design Departmen......

asked by ray.anderson

the difference between the pkg/die model in activ......

Hi, experts,During the effort trying to correlate the channel simulation result to the test result, ......

asked by sherman.chen lastest answer by weirsi