Specification (often abbreviated as spec) may refer to an explicit set of requirements to be satisfied by a material, design, product, or service.
How to specify via hole sizes
One thing that has bothered me forever is the ambiguity in specifying viahole sizes. To my mind, the......
asked by jeff.loyer lastest answer by buenoshun
0
votes
critical insetion loss at 4GHz for PCIe 3
Hi experts,I have a question that "PCI Express® Base Specification Revision 3.0" hasno illustration......
asked by zhangjun5960 lastest answer by stevenzhaozhenwei
0
votes2
answers
Boards, Chips and Packaging Seminar, October 13
The below one day conference has been organized to deal with the problemsassociated with interacting......
asked by leeritchey
0
votes0
answers
Opening in Molex Singapore
Fellow SI engineers,I am looking to hire a senior person in my team in Singapore. Please see the det......
asked by dmarc-noreply
0
votes0
answers
HDMI or DP EMI issue
Dear all,I am studying HDMI or DP EMI issue.One curiosity is Spread spectrum specifications of HDMI ......
asked by dmarc-noreply-outsider lastest answer by keith.hardin
0
votes5
answers
DDR4 and PAM4 DesignCon papers
Hi si-listers,I uploaded our DesignCon 2015 technical track papers to:http://signal-integrity.blogs.......
asked by colin_warwick
0
votes0
answers
Pin vs. Die
Historically, when performing PCB SI (ibis) simulations I've always focused on the SI quality of a s......
asked by conrad.herse lastest answer by dmarc-noreply
0
votes19
answers
Job Description for Project Signal Integrity Engr......
Bob Savatovic here again . . . earlier today I had posted the Project Signal Integrity Engr positi......
asked by dmarc-noreply
0
votes0
answers
switch mode power supply noise (class D amps as w......
Hi All,I am going to present a one hour web session next Thursday, October 30th on a problem a lot o......
asked by doug
0
votes0
answers
High Speed Interconnect Technologist needed in Sa......
High Speed System Interconnect TechnologistJob Description;1) Analyze the high speed digital interc......
asked by Mark.Apton
0
votes0
answers
Pcie PLL bandwidth
Hello,I am validating chip-chip pcie gen 1 interface.My design has pcie linkbetween CPUASIC and CPUF......
0
votes4
answers
IBIS Summit at DAC 2014 - Final Call for Presenta......
The IBIS Open Forum is holding an IBIS Summit meeting as a colocated conference at the Design Automa......
asked by michael.mirmak
0
votes0
answers
Openings in Molex (Singapore)
GuysThere are couple of openings in Molex Singapore for Signal Integrity Engineers with Design and A......
asked by satishp
0
votes0
answers
DDR3 Ccomp capacitance delay
Hi Experts,SODIMM and controller specifications I read all say to match (in time) address/command ne......
asked by petebenjamin730 lastest answer by brahimkou
0
votes5
answers
Regarding AC Input test conditions and Slew rate ......
When i am reading DDR2 specifications,i got 2 different definitions for input signal slew rate , one......
asked by malli.1729 lastest answer by ferhatyaldiz
0
votes1
answers
Free Margin
I've been pondering a few past and recent discussions about particular SIdesign techniques. I know ......
asked by scott
0
votes0
answers
Announcing IBIS Version 6.0!
The IBIS Open Forum is pleased to announce that IBIS Version 6.0 was approved September 20 and is no......
asked by michael.mirmak
0
votes0
answers
Vacancy for Principal in High Speed Interconnect ......
Candidate for this position should be at least Bachelor with 15+ years, or M.S.E.E. with 10+ years, ......
asked by jinzhaoguo
0
votes0
answers
Measurement point for DDR3
Hi experts,I am validating pre-silicon an embedded DDR3 interface with simulation. The system is an ......
asked by ted.clark lastest answer by yousufs432
0
votes10
answers
Signal Integrity Technical Marketing Engineer - J......
Job Title[https://xapps9.xilinx.com/OA_HTML/cabo/images/swan/t.gif]Signal Integrity Technical Market......
asked by romi.mayder
6
answers