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IBIS simulations using the datasheet reference loa......


Hello experts,I'm a newbie with SI simulation, this is my first attempt. Right now I'm designing the......

asked by mpat.cohen.sch

4 years 1 month 20 days

0

votes

0

answers
2927 views

Serpentine line self-crosstalk simulation in Hype......


?/ÞÆ?«¶Â0j{m¢Ç?¶­?gzV²jwl?    Ú?«??+r?jZrםo+®?§¶)Þ?)Þ¥«mz¹ìr§çÿëb¶Ç??Éèr§ë¢éÝ?qò¥êåÊ|l?k¥j......

asked by aleilee2008 lastest answer by Charles.Grasso

4 years 1 month 17 days

0

votes

13

answers
4516 views

Seminar: 4 Essential Steps for EDA Simulation-Mea......


Yuriy Shlepnev and Wild River Technology will be delivering a high technical presentation:4 Essentia......

asked by al lastest answer by shlepnev

4 years 3 months 7 days

0

votes

1

answers
1932 views

The margin of IBIS-AMI Serdes simulation


Hi Expertsi am doing a medium loss 10Gbps channel IBIS-AMI simulation. The channel loss is 15dB at 5......

asked by emcesd lastest answer by al

4 years 4 months 4 days

0

votes

3

answers
2744 views

Seminar Invite: Getting Ahead with High Speed Dig......


SI-List folks,  Thought everyone might like to know that WRTâ??s Alfred Neves and CSTâ??s Klaus Kron......

asked by al

4 years 4 months 4 days

0

votes

0

answers
1859 views

Webinar: Co-optimizing Tx/Rx parameters in IBIS-A......


Hi all, SiSoft is offering a free webinar next Tuesday (Feb 23) on co-optimizingTx/Rx parameters to ......

asked by twesterh

4 years 4 months 16 days

0

votes

0

answers
1814 views

Power Supply Noise injected Jitter impact on SERD......


Hi All,In my design I have high speed interfaces like DDR4 and PCIe 3.0 interfaceoperating at their ......

asked by rameshp3note lastest answer by carsona

4 years 6 months 22 days

0

votes

1

answers
2233 views

Job Opening at Qualcomm: Signal Integrity Enginee......


Hello,Qualcomm Package Electrical Group has a Job opening in San Diego, CA for a qualified Candidate......

asked by moshiulh

4 years 6 months 22 days

0

votes

0

answers
2264 views

Fwd: VRM bode plot transformation into output imp


---------- Forwarded message ----------From: Don Pakbaz Date: Wed, Jan 13, 2016 at 8:43 AMSubject: V......

asked by don.pakbaz

4 years 6 months 23 days

0

votes

0

answers
2185 views

VRM bode plot transformation into output imp prof......


Hi,This post is about theories on VRM modelling.For power integrity analysis ideally we should combi......

asked by buenoshun lastest answer by jun.zhou

4 years 6 months 23 days

0

votes

13

answers
4089 views

Influence of 8b10 encoder to eye diagram


Hi experts,In simulation of SAS-3 12Gbps by IBIS-AMI model obtained from vendors, Iaccidently compar......

asked by zhangjun5960 lastest answer by vladimir_dmitriev-zdorov

4 years 6 months 7 days

0

votes

11

answers
4060 views

ground recessing


Hi experts,I approach a case about ground recessing. For eight PCIE lanes, the sixteenAC caps are in......

asked by zhangjun5960 lastest answer by leeritchey

4 years 6 months 13 days

0

votes

16

answers
3741 views

redriver issue


Hi all,I think redriver is an old and still difficult topic.we approach in simulation, redriver can ......

asked by zhangjun5960 lastest answer by zhangjun5960

4 years 7 months 25 days

0

votes

9

answers
3983 views

Creating S parameter model for simulation


Hello Experts,I would like to study the impact of different routing on mounted inductance for decoup......

asked by benoit.goral lastest answer by istvan.novak

4 years 7 months

0

votes

1

answers
2431 views

Impact of pad cap on return loss


Hello Experts,I am designing a package for a 12 Gbps Serdes.The package layout is showing a differen......

asked by amit.j.kumar lastest answer by al

4 years 7 months 10 days

0

votes

6

answers
3100 views

High Speed I/O Signal Integrity Engineer with IDT......


Title: Staff Signal Integrity EngineerAs a High Speed I/O Signal Integrity Engineer, you will be res......

asked by Yue.Yu

4 years 8 months 27 days

0

votes

0

answers
2028 views

Reg :Altera Encrypted Hspice simulation


Dear all,We are using Altera Fpgs in our design.We are doing Signal integrity forthe design.Altera p......

asked by gkravi.1988 lastest answer by Arpad_Muranyi

4 years 8 months 7 days

0

votes

1

answers
1996 views

Call for Papers - 2016 IEEE 20th Workshop on Sign......


Dear Members,The 2016 IEEE 20th Workshop on Signal and Power Integrity (SPI) will beheld from May 8 ......

asked by dmarc-noreply

4 years 8 months 12 days

0

votes

0

answers
2032 views

Ref. for CSDF?


Hi all,Does anyone have a reference for CSDF (Common Simulation Data Format) files and/or know of a ......

asked by DBanas lastest answer by Joseph.Schachner

4 years 8 months 18 days

0

votes

2

answers
2080 views
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