A step in the design of printed circuit boards (PCBs) and integrated circuits (ICs). It builds on a preceding step, called placement, which determines the location of each active element of an IC or c

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Routing High-Speed differential signals on top and......


Hi,I plan to design aboard with 10 Gbps (~35 ps rise/fall time) transceiver.TI High-Speed InterfaceL......

asked by MegaOhm lastest answer by Old_School

4 years 3 months 1 day

0

votes

1

answers
3956 views

Generic vs. specific stackups for PCB designers


I have a question targeted at the design and signal integrity engineersâ??perspective, not PCB fabri......

asked by jeff.loyer lastest answer by buenoshun

4 years 9 months 20 days

0

votes

2

answers
3825 views

min trace length


Hi experts,As we know, there are two kinds of applications for DDR, one is SDRAM onboard, and anothe......

asked by chambers.yin lastest answer by chambers.yin

4 years 9 months 12 days

0

votes

4

answers
2547 views

Creating S parameter model for simulation


Hello Experts,I would like to study the impact of different routing on mounted inductance for decoup......

asked by benoit.goral lastest answer by istvan.novak

4 years 9 months 13 days

0

votes

1

answers
2589 views

RegardingDual Stripline PCB routing


HiI am planning to design a PCB board using Dual Stipline. The board has several high speed interfac......

asked by VIVEK.VISHWANATH lastest answer by scott

5 years 11 days

0

votes

3

answers
2271 views

Skew vs length matching


Hello guys,I am making a board using a FPGA whose serdes runs on 12.5 Gbps.Owing to the FPGA ball ma......

asked by amit.j.kumar lastest answer by jpnathan

5 years 4 months 12 days

0

votes

2

answers
2419 views

Channel deterministic jitter


Ignoring for this discussion the active Tx / Rx components of a (high speedSERDES) channel, and cons......

asked by ralph.wilson lastest answer by al

5 years 6 months 26 days

0

votes

4

answers
2076 views

Hyperlynx far end crosstalk simulation issue


Sorry for the messy code. Have no idea what happened. Resent this email...Hi experts,It's known that......

asked by lmt8885 lastest answer by jeff.loyer

5 years 6 months 5 days

0

votes

7

answers
3448 views

Question on USB 2.0


Dear techies,I have a question on USb 2.0. We have one of our custom SoC having USBTransceiver funct......

asked by chundis lastest answer by vijaychachra

5 years 8 months 22 days

0

votes

2

answers
2240 views

Glass-Weave Skew / Fiber-Weave Effect


Hi Folks …I’m doing a bit of research on glass-weave skew / the fiber-weave effect. I’ve read the a......

asked by billh

5 years 9 months 20 days

0

votes

0

answers
1768 views

Uncoupled differential signalling


On a recent design I tried out routing loosely coupled differential pairs.Previous tests I've have d......

asked by johan.lans lastest answer by johan.lans

5 years 10 months 27 days

0

votes

3

answers
2508 views

Ground vias and the land of ID ("It Depends")


At the risk of finding myself embroiled in a furball, I thought I'd see if I could clear up (in my o......

asked by jeff.loyer lastest answer by scott

5 years 11 months 4 days

0

votes

5

answers
2586 views

Intel is looking for an SI Engineer in Hillsboro,......


Job Description: Designs, develops, evaluates, and validates high speed signaling interfaces on Inte......

asked by gene.garrison

5 years 11 months 6 days

0

votes

0

answers
1777 views

impedance determination of a perticular interface......


Hi,I have seen specifying routing impedance of interfaces from Manufacturerslike forUSB Differential......

asked by malli.1729 lastest answer by colin_warwick

6 years 9 days

0

votes

3

answers
2554 views

about connector models and backplane


Hello experts.I need to simulate some PCBs (space application) mounting high reliability connectors ......

asked by pietrov

6 years 1 month 14 days

0

votes

0

answers
1712 views

source of DDR 4 timing recommendations


Can anyone help me understand the source of the pcb routing recommendationsI see for DDR4. For inst......

asked by ericsilist lastest answer by Nitin_Bhagwath

6 years 1 month 26 days

0

votes

6

answers
2486 views

Use of Ccomp capacitor in DDR clock


Hi all, We have discussed lot on DDR3 clock termination techniques & routing,but I guess we haven......

asked by bala89si

6 years 4 months 12 days

0

votes

0

answers
1992 views

Clarification on Trace Routing over Plane Splits


Hi all -I have previously spent time in the high-speed realm, routing PCIe,SATA, HT, and many other ......

asked by movax lastest answer by movax

6 years 6 months 4 days

0

votes

4

answers
2572 views

DDR3 Clarification


Hi,I have a doubt.I have a processor and 4 DDR3 IC's.U1 - ProcessorU3 - D0-15U4 - D16-31U5 - D32-47U......

asked by shankar-v

6 years 6 months 17 days

0

votes

0

answers
1598 views

Impact on Copper Thieving on 10G Routing


Hi Experts,What are the major impact created by Copper Thieving in the 10G signals and the precautio......

asked by sij99 lastest answer by Gert.Havermann

6 years 6 months 24 days

0

votes

6

answers
3275 views
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