providing a terminator at the end of a wire or cable to prevent an RF signal from being reflected back from the end.

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Re: si-list Digest V16 #24


A few things to recognize, folksFirst, ANYONE can build an averaged model which is state space plane......

asked by Steve lastest answer by Steve

4 years 7 months 24 days

0

votes

3

answers
3224 views

Impact of pad cap on return loss


Hello Experts,I am designing a package for a 12 Gbps Serdes.The package layout is showing a differen......

asked by amit.j.kumar lastest answer by al

4 years 8 months 11 days

0

votes

6

answers
3165 views

Looking for appropriate forum/mailing list for ES......


Dear Experts,I have been a long time follower of the mailing list and I have thoroughlyenjoyed readi......

asked by alfred1520list

4 years 9 months 12 days

0

votes

0

answers
1837 views

Serdes Queries


Hi All,I have some queries w.r.t. Serdes.1. Ideally CDR transfer function -3dB corner freq(Low pass ......

asked by bhavanipadhi lastest answer by bhavanipadhi

5 years 1 month 9 days

0

votes

2

answers
2154 views

LVDS 2.5V Vcm(common mode) simulation measurement......


Hi experts,I have a board with 100MHz oscillator LVDS 2.5V *AC coupled* with 100nFcapacitors to cloc......

asked by waqaschaudharyciit lastest answer by telegrapher9

5 years 4 months 11 days

0

votes

11

answers
3078 views

Question on USB 2.0


Dear techies,I have a question on USb 2.0. We have one of our custom SoC having USBTransceiver funct......

asked by chundis lastest answer by vijaychachra

5 years 7 months 10 days

0

votes

2

answers
2144 views

S-Parameter view for multiDrop bus


Hello Experts,I struggeled with this one several times in the past and maybe somebodyhas some answer......

asked by Hermann.Ruckerbauer lastest answer by Hermann.Ruckerbauer

5 years 8 months 2 days

0

votes

5

answers
2995 views

DDR2 problem


Having some issues with a 225MHz DDR2 implementation at high temperature.I am wondering if the probl......

asked by bryan lastest answer by Hermann.Ruckerbauer

5 years 9 months 12 days

0

votes

3

answers
2048 views

Re: si-list Digest V14 #214


Joel,In addition to Steve's reference to 802.3ap, I would also refer you to ANSIVITA 46.6 (if you ha......

asked by eric.tollefson lastest answer by sherman.chen

5 years 11 months 27 days

0

votes

1

answers
1874 views

EMI Filters on I/O Lines & Impedance Matching


Hi,It is often usual to see something like a PI-filter (C-L-C) filter on I/Osignal lines in an attem......

asked by carson.au lastest answer by HUBING

6 years 1 month 13 days

0

votes

6

answers
2198 views

Termination of unused Ethernet pairs


HiI've got an board with 10/100 Ethernet on it and we have no margin inconducted emissions tests for......

asked by james.dowle lastest answer by leeritchey

6 years 1 month 28 days

0

votes

1

answers
1778 views

ddr3 Vtt sso issue


In our test setup we measured a surge of up to 500mV on Vtt when all addresses switch  (qty = 20) fr......

asked by dmarc-noreply lastest answer by paul.taddonio

6 years 2 months 3 days

0

votes

5

answers
2298 views

DDR3 on die termination and ZQ


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asked by jinfeng

6 years 2 months 28 days

0

votes

0

answers
1735 views

Use of Ccomp capacitor in DDR clock


Hi all, We have discussed lot on DDR3 clock termination techniques & routing,but I guess we haven......

asked by bala89si

6 years 3 months

0

votes

0

answers
1883 views

Termination Regulator - Help


Hi,All DDR memories uses source / sink termination regulator.Please let me know the usage of this (F......

asked by mani.kumar lastest answer by yonghui.sky

6 years 3 months 1 day

0

votes

1

answers
1724 views

[SI-List]: Current Vs Voltage transmission for be......


Hi All,I have a basic query on usage of current waveform or voltage waveform fortransmission of sign......

asked by ah.vinod lastest answer by weirsi

6 years 3 months 15 days

0

votes

4

answers
1924 views

ODT termination - LPDDR2


Hi,Understanding of ODT in architecture of one LPDDR2 interfaced with FPGA:Please guide me on ODT : ......

asked by mani.kumar lastest answer by paul.taddonio

6 years 3 months 17 days

0

votes

2

answers
2505 views

need advice on DDR3 simulation / termination


I am working on a DDR3 design. It uses an older FPGA (Altera Arria II GX) which does does not suppor......

asked by joel lastest answer by ken

6 years 3 months 22 days

0

votes

14

answers
2059 views

DDR3 termination on address / control lines


In my design there are two DDR3 chips on the boards.Is it better to use a fly by termination or T wi......

asked by joel lastest answer by gnuarm.2006

6 years 3 months 24 days

0

votes

3

answers
1794 views

termination on cpci


Hello expert.Reading document PICMG 2.0 R3.0 (Oct 1999), I see Compact PCI "standard" assumes many b......

asked by pietrov lastest answer by weirsi

6 years 4 months 20 days

0

votes

2

answers
2115 views
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