the receiving end of a communications channel

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differential signal driver\ receiver


Hello,The diffrerantial communication spec:The Lines: H,LVoltage levels: 0-5vLogic:True: H =5v ,L =0......

asked by shimonakrish

4 years 11 months 13 days

0

votes

0

answers
2242 views

Re: Necessity of considering Pin Delay for Length......


Hi,Any of your signals set off from your driver's die not pin,usually we measure timing at receiver ......

asked by balaseven

5 years 2 months 4 days

0

votes

0

answers
1827 views

Serdes Queries


Hi All,I have some queries w.r.t. Serdes.1. Ideally CDR transfer function -3dB corner freq(Low pass ......

asked by bhavanipadhi lastest answer by bhavanipadhi

5 years 3 months 19 days

0

votes

2

answers
2288 views

Hyperlynx far end crosstalk simulation issue


Sorry for the messy code. Have no idea what happened. Resent this email...Hi experts,It's known that......

asked by lmt8885 lastest answer by jeff.loyer

5 years 7 months 2 days

0

votes

7

answers
3508 views

Serdes Rx Jitter Tolerance


Once again I come with hat in hand to solicit for opinions from those who'll indulge me, I'm interes......

asked by conrad.herse lastest answer by al

5 years 7 months 11 days

0

votes

8

answers
2447 views

How to Reasonably Correlate The SAS 12G Signal In......


Dear Experts,The SAS 12G signals correlation issues are haunting us in recent projects.And I would l......

asked by leomhc718 lastest answer by sherman.chen

5 years 7 months 12 days

0

votes

1

answers
2328 views

Tap settings on IBIS AMI models


Hi Experts,I'm working with serdes ibis ami simulation. Can anyone guide me ,how to select optimum p......

asked by sureshkumar.ayyavu lastest answer by DBanas

5 years 7 months 12 days

0

votes

2

answers
3023 views

about the built in resistance


hi,all: I have a problem recently,in my application,a lvpecl driver interfaces with a cml receive......

asked by edisonzheng lastest answer by conrad.herse

5 years 9 months 6 days

0

votes

1

answers
1853 views

SigNoise errors/warnings during simulation


We are trying to simulate a topology.Driver is MPC8349EHere are the Models available for DDR2. ddr2_......

asked by malli.1729 lastest answer by malli.1729

5 years 11 months 17 days

0

votes

2

answers
2072 views

Point to point simulation results


Hi,I am trying to simulate a topology.it consists of driver --> 0 ohm resistor --> MS line (length v......

asked by malli.1729 lastest answer by sherman.chen

6 years 2 days

0

votes

3

answers
2174 views

questions related to of OIF-CEI-11G LR/MR


Hello Experts,I have two questions related to OIF-CEI-11GLR/MR standards:1) The standard define......

asked by amit.j.kumar

6 years 14 days

0

votes

0

answers
2041 views

Webcast: How to Optimize Your SerDes Design Durin......


Hello,I'm giving a webcast next week entitled "How to Optimize Your SerDes Design During the Pre-lay......

asked by colin_warwick

6 years 1 month 6 days

1

votes

0

answers
2208 views

Re: One stitching via or more vias is better for ......


On 9/7/2014 8:49 PM, leeritchey@xxxxxxxxxxxxx wrote:> All of the things proposed don't seem to have ......

asked by DBanas lastest answer by scott

6 years 1 month 15 days

0

votes

3

answers
2437 views

Default tap settings for SerDes


For SerDes transceivers with high equalization capabilites and manydifferent tap combinations, when ......

asked by marioantolos lastest answer by ransom

6 years 1 month 21 days

0

votes

3

answers
1847 views

understanding acceptable amount of jitter for giv......


Hi all, I'm having trouble trying to understand how to define what anacceptable amount of jitter......

asked by ericsilist lastest answer by ajay.dhingra

6 years 1 month 26 days

0

votes

4

answers
2205 views

Replacement for Sumitomo FHX35X/002


Hi,I have been using Sumitomo (was FUJITSU) FHX35X/002 a low leakage, low capacitance, high Ft & hig......

asked by yoram.porat

6 years 4 months 14 days

0

votes

0

answers
1646 views

Maximum trace length of PCIE 3.0 REFCLK in addin ......


Hi,I want to know is there any maximum trace length routed in Add-in card forPCIE_REFCLK (*PCI expre......

asked by malli.1729 lastest answer by Chris.Cotton

6 years 5 months 11 days

0

votes

8

answers
2534 views

[SI-List]: Current Vs Voltage transmission for be......


Hi All,I have a basic query on usage of current waveform or voltage waveform fortransmission of sign......

asked by ah.vinod lastest answer by weirsi

6 years 5 months 24 days

0

votes

4

answers
2048 views

need advice on DDR3 simulation / termination


I am working on a DDR3 design. It uses an older FPGA (Altera Arria II GX) which does does not suppor......

asked by joel lastest answer by ken

6 years 6 months 1 day

0

votes

14

answers
2193 views

termination on cpci


Hello expert.Reading document PICMG 2.0 R3.0 (Oct 1999), I see Compact PCI "standard" assumes many b......

asked by pietrov lastest answer by weirsi

6 years 6 months 29 days

0

votes

2

answers
2258 views
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