undesired deviation from true periodicity of an assumed periodic signal in electronics and telecommunications, often in relation to a reference clock source.

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Measure RMS jitter of Serdes using spectrum analy......


Hi ExpertsI am curious about a idea using spectrum analyzer to measure the RMS jitter of serdes. Bec......

asked by emcesd lastest answer by emcesd

4 years 8 months 27 days

0

votes

7

answers
2525 views

Power Supply Noise injected Jitter impact on SERD......


Hi All,In my design I have high speed interfaces like DDR4 and PCIe 3.0 interfaceoperating at their ......

asked by rameshp3note lastest answer by carsona

4 years 9 months 2 days

0

votes

1

answers
2442 views

Panelist needed for DesignCon 2016


Greetings,For DesignCon 2016, I'm organizing a panel session around measurements on PAM4 modulation.......

asked by martin.rowe

5 years 28 days

0

votes

0

answers
1850 views

100base-TX Ethernet RXP/RXN pins bit interval or ......


Hi all,I am working on 100base-TX ethernet configuration.Can any body tell,What isthe Minimum bit in......

asked by gkravi.1988 lastest answer by gkravi.1988

5 years 12 days

0

votes

1

answers
2114 views

10G SERDES issue


Hi All,We have 10G SERDES channel between ASIC(MAC switch) and phy and there is noissues if we initi......

asked by balaseven lastest answer by alan.hiltonnickel

5 years 1 month 24 days

0

votes

2

answers
2184 views

Serdes Queries


Hi All,I have some queries w.r.t. Serdes.1. Ideally CDR transfer function -3dB corner freq(Low pass ......

asked by bhavanipadhi lastest answer by bhavanipadhi

5 years 3 months 19 days

0

votes

2

answers
2288 views

[SI-LIST]: PCIe2 Rx Eye Spec inside Pad


Hi All,I was trying to measure BER contour (Eye) inside PCIe2 Rx after CTLE-CDR,not on RX pins.I see......

asked by ah.vinod lastest answer by Joseph.Schachner

5 years 5 months 2 days

0

votes

1

answers
2170 views

Channel deterministic jitter


Ignoring for this discussion the active Tx / Rx components of a (high speedSERDES) channel, and cons......

asked by ralph.wilson lastest answer by al

5 years 6 months 22 days

0

votes

4

answers
2121 views

Serdes Rx Jitter Tolerance


Once again I come with hat in hand to solicit for opinions from those who'll indulge me, I'm interes......

asked by conrad.herse lastest answer by al

5 years 7 months 11 days

0

votes

8

answers
2447 views

Mastering High Speed Serial Tech Class -


Hi everyone, A quick note to let you know that I'm teach classes on high speed serialtech in Penang ......

asked by ransom

5 years 7 months 17 days

0

votes

0

answers
2103 views

Question about jitter at serdes transmitter


We are using an Altera Arria II GX FPGA for a SATA 3 6GBPS interface.I ran some simulations in Hspi......

asked by joel lastest answer by dmarc-noreply

5 years 8 months 8 days

0

votes

4

answers
2863 views

PCIe 3.0 Clock Jitter Tool


I am looking for PCIe 3.0 Clock Jitter Compliance measurement  tool. Read about many are using Inte......

asked by dmarc-noreply lastest answer by Joseph.Schachner

5 years 8 months 9 days

0

votes

442

answers
3326 views

Clock Jitter Compliance measurement  tool


Ashish,They (Intel) will not share this tool unless you are engaged, in someway, with the team that'......

asked by sio2man1

5 years 8 months 10 days

0

votes

0

answers
2041 views

Re: PCIe Gen3 DMSI calibration concept ... RX tes......


Hi, Boris. My opinion is: 1) It makes sense to test at that calibrated state, that is really the ca......

asked by Joseph.Schachner

5 years 9 months 14 days

0

votes

0

answers
2049 views

Eye-diagram FUSS metric


I've searched everywhere to no avail trying to find out what the meaning of the abbreviation 'FUSS' ......

asked by ray.anderson

5 years 11 months 12 days

0

votes

0

answers
1723 views

questions related to of OIF-CEI-11G LR/MR


Hello Experts,I have two questions related to OIF-CEI-11GLR/MR standards:1) The standard define......

asked by amit.j.kumar

6 years 14 days

0

votes

0

answers
2041 views

Single ended Noise OR Differential Noise


Hi folks,I am doing power noise analysis on a system that uses SSTL IO buffers. Iam seeing the rippl......

asked by naresh.dhamija lastest answer by skgupta.sanjeev

6 years 16 days

0

votes

11

answers
1882 views

bit inversion in DDR3


Hello experts.DDR4 has got new feature of bit-inversion to control SSN jitteris it possible to imple......

asked by dmarc-noreply lastest answer by Hermann.Ruckerbauer

6 years 25 days

0

votes

1

answers
2074 views

free Teledyne LeCroy jitter webinar with Bogatin ......


Not too late to register for our free webinar on Tues Sept 9: EssentialPrinciples of Jitter, part 3.......

asked by eric lastest answer by lyndell.l.asbenson

6 years 1 month 15 days

0

votes

1

answers
1555 views

Senior SI engineer and internship position availa......


Hi there,I am the hiring manager so please send me your resume directly.The intern position is in Fr......

asked by chris.cheng

6 years 1 month 19 days

0

votes

0

answers
1666 views
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