redriver issue

Hi all,I think redriver is an old and still difficult topic.we approach in simulation, redriver can ......

Loss Insertion Loss Timing Simulation PCI PCIE

asked by zhangjun5960 lastest answer by zhangjun5960

5 years 1 month 4 days

0

votes

9

answers

4517 views

DDR3 output timing uncertainty question.

Hi all,How does one estimate the relative output timing uncertainty, between DQ and DQS, for a DDR3 ......

Timing DDR DDR3

asked by DBanas lastest answer by John.Ellis

5 years 4 months 23 days

0

votes

7

answers

3782 views

Necessity of considering Pin Delay for Length mat......

Hi All,We're using Cadence PCB Designer for our Layout design. Wherever we're doing length matching ......

PCB Timing Cadence

asked by kishorekumar.moh lastest answer by ivanperino

5 years 5 months 4 days

0

votes

2

answers

2027 views

Ac threshold timings

Hi ExpertsHere's my question.In ddr3 simulation I have come across AC175, AC150 & AC135.I have confu......

Timing Simulation DDR DDR3 Standard measurement

asked by kalyan.krishnan02 lastest answer by kalyan.krishnan02

5 years 9 months 5 days

0

votes

5

answers

4005 views

AC timing analysis

Hi All, Do anybody is having idea about AC timing analysis , for interfacing to highspeed interface ......

Timing Timing Analysis

asked by parveen.rao lastest answer by parveen.rao

5 years 9 months 23 days

0

votes

2

answers

1934 views

Cisco Job Opening - Senior Signal Integrity Engin......

Hi,Can you please post to your site? Applicants can apply at https://jobs.cisco.com/job/San-Jose-Sen......

asked by Steven Goloskov -X (sgolosko - RANDSTAD NORTH AMERICA LP at Cisco)"

5 years 10 months 25 days

0

votes

0

answers

2922 views

Please Post - Cisco Sr. Hardware Engineer

Hi,Can you please post to your site? Applicants can apply at https://jobs.cisco.com/job/San-Jose-Sen......

asked by Steven Goloskov -X (sgolosko - RANDSTAD NORTH AMERICA LP at Cisco)" lastest answer by Steven Goloskov -X (sgolosko - RANDSTAD NORTH AMERICA LP at Cisco)"

5 years 10 months 26 days

0

votes

1

answers

3505 views

reduce xtalk thru polarity reversal

Hi experts,I got a question about minimizing xtalk by reversing the polarity.As you know, if all po......

Timing

asked by sherman.chen lastest answer by scott

5 years 10 months 11 days

0

votes

2

answers

1847 views

DDR3 DQ-DSQ skew over temperature

Dear all,In read leveling procedure DQS and DQ signals are aligned in the controllerso that optimum ......

Voltage Timing DDR DDR3 Skew Calibration

asked by bbakshan lastest answer by Hermann.Ruckerbauer

6 years 13 days

0

votes

1

answers

2526 views

Job Description for Project Signal Integrity Engr......

Bob Savatovic here again . . . earlier today I had posted the Project Signal Integrity Engr positi......

asked by dmarc-noreply

6 years 13 days

0

votes

0

answers

2686 views

DDR3 16bit interfaces

Hello all,I would like to ask your help with the following:With 16bit DRAM interfaces we have both U......

Timing DDR DDR3

asked by bbakshan lastest answer by Hermann.Ruckerbauer

6 years 1 month 1 day

0

votes

1

answers

2260 views

Signal Integrity Engineer position at Juniper Net......

Hi,We have an opening for SI Engineer at Juniper Networks, Sunnyvale, CA.If you are interested, plea......

PCB SerDeS Transmission Line Noise Clock Timing Timing Analysis Simulation DDR Spectrum Spectrum Analyzer Oscilloscope HFSS ADS Sigrity Allegro Signal Integrity measurement

asked by russel.ataul

6 years 1 month 13 days

0

votes

0

answers

2168 views

timing in s-parameters

I know in a simple way that S-parameters are a frequency domainrepresentation of how much of the sig......

connector Timing Simulation

asked by ericsilist lastest answer by piero.triverio

6 years 4 months 18 days

0

votes

9

answers

1997 views

source of DDR 4 timing recommendations

Can anyone help me understand the source of the pcb routing recommendationsI see for DDR4. For inst......

PCB Package Clock Timing Routing Simulation DDR DDR4 Standard JEDEC

asked by ericsilist lastest answer by Nitin_Bhagwath

6 years 5 months 22 days

0

votes

6

answers

2680 views

SI opportunity at Synopsys, Bangalore

Dear SI-list usersWe have 2 open reqs. for SI engineers at Synopsys, Bangalore location. If you are ......

Package Timing Simulation Decoupling Power Delivery Network DDR Signal Integrity Power Integrity

asked by dmarc-noreply

6 years 7 months 8 days

0

votes

0

answers

2107 views

PCIe Gen 3 Compliance Pattern

How Long is the Compliance Pattern for PCIe Gen 3?The spec lists several different types of complian......

Timing PCI PCIE Compliance

asked by gedlund lastest answer by gedlund

6 years 9 months 9 days

0

votes

4

answers

1894 views

Purpose of Cref,Rref and Vref parameters in IBIS ......

Hi,from IBIS spec"The Cref and Rref subparameters correspond to the test load| that the semiconducto......

IBIS Reference Current Voltage Timing Simulation measurement

asked by malli.1729 lastest answer by weirsi

6 years 9 months 28 days

0

votes

2

answers

2480 views

DDR3-1600 Double-Tee Topology

Hi Everyone,Has anyone tried using a double-tee topology with their address/command/control signals ......

Clock Loss Insertion Loss Timing Simulation DDR DDR2 DDR3 DIMM Eye Eye diagram Standard

asked by josephaday lastest answer by prashant.jaiswar

7 years 12 days

0

votes

19

answers

3577 views

DDR3 Ccomp capacitance delay

Hi Experts,SODIMM and controller specifications I read all say to match (in time) address/command ne......

Clock Capacitance Timing Specification DDR DDR3 DIMM

asked by petebenjamin730 lastest answer by brahimkou

7 years 1 month 9 days

0

votes

5

answers

2747 views

Cref and Rref -Ibis model vs datasheet

Hi,This is regarding ibis model parameters.The parameters Vmeas, Cref, Rref, Vref are optionalâ??Ref......

IBIS Timing Simulation Signal Integrity measurement

asked by kbmanick lastest answer by ferhatyaldiz

7 years 1 month 17 days

0

votes

2

answers

1634 views