In electronics and especially synchronous digital circuits, a clock signal is a particular type of signal that oscillates between a high and a low state and is utilized like a metronome to coordinate
clock ATMEL AT91SAM9260
hi, anyone has worked with ATMEL AT91SAM9260, in particular for compliance with the radiated Emissio......
asked by dopatissimo lastest answer by Old_School
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votes
Wiring Harnessing SI Question
HI all --Hoping that list can shed some light on some wire harness related SIquestions at some very,......
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votes4
answers
Looking for appropriate forum/mailing list for ES......
Dear Experts,I have been a long time follower of the mailing list and I have thoroughlyenjoyed readi......
asked by alfred1520list
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votes0
answers
10G SERDES issue
Hi All,We have 10G SERDES channel between ASIC(MAC switch) and phy and there is noissues if we initi......
asked by balaseven lastest answer by alan.hiltonnickel
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votes2
answers
Why do we still TDR pcbs
 Hi folks,See lots of discussion this month on whether SI has become commoditized. I'll hold off ......
asked by dmarc-noreply lastest answer by al
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votes9
answers
Longer SATA tx (host to drive) transfers issue
Hi everyone,I have a new version of a board of ours on which Ihave put Marvells 88sa8052 ATA SATA b......
0
votes1
answers
Phase or Frequency drift when hiting a cable
Cable convey 10Mhz from a ultrastable clock STALO to the PLL using lvds.PLL output is 1275Mhz and it......
asked by ivanperino
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votes0
answers
Serdes Queries
Hi All,I have some queries w.r.t. Serdes.1. Ideally CDR transfer function -3dB corner freq(Low pass ......
asked by bhavanipadhi lastest answer by bhavanipadhi
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votes2
answers
Anti Pads in Differential Pairs
Hello Experts,The benefits of antipads in high speed differential pairs signals are known.But I see ......
asked by sergio lastest answer by Chris.Cotton
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votes1
answers
LVDS 2.5V Vcm(common mode) simulation measurement......
Hi experts,I have a board with 100MHz oscillator LVDS 2.5V *AC coupled* with 100nFcapacitors to cloc......
asked by waqaschaudharyciit lastest answer by telegrapher9
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votes11
answers
Serdes Rx Jitter Tolerance
Once again I come with hat in hand to solicit for opinions from those who'll indulge me, I'm interes......
asked by conrad.herse lastest answer by al
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votes8
answers
Mastering High Speed Serial Tech Class -
Hi everyone, A quick note to let you know that I'm teach classes on high speed serialtech in Penang ......
asked by ransom
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votes0
answers
PCIe 3.0 Clock Jitter Tool
I am looking for PCIe 3.0 Clock Jitter Compliance measurement  tool. Read about many are using Inte......
asked by dmarc-noreply lastest answer by Joseph.Schachner
0
votes442
answers
Clock Jitter Compliance measurement  tool
Ashish,They (Intel) will not share this tool unless you are engaged, in someway, with the team that'......
asked by sio2man1
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votes0
answers
[SI-List]: Spread Spectrum Modulation Rate
Hi All,This query is with respect to Spread spectrum clocking/PLL design.We see that modulation rate......
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votes1
answers
Signal Integrity Engineer position at Juniper Net......
Hi,We have an opening for SI Engineer at Juniper Networks, Sunnyvale, CA.If you are interested, plea......
asked by russel.ataul
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votes0
answers
Calculating Zin for a DSP Clock
Hi Experts,I'm trying to calculate the Zin for the CLK in the ADSP21469.As far as I know I can use t......
asked by jesuscastanemnez lastest answer by HUBING
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votes9
answers
Oscilloscope bandwidth and Non_Monotonic
Hi All,I am measuring 125MHZ,1.2ns rise time clock with Tek's scope.When i measure clock with 5G Ban......
asked by balaseven lastest answer by goswamisurjendra
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votes3
answers
Re: Oscilloscope bandwidth and Non-Monotonic
BalaThe clock may toggle at 125 MHz and the edge rate at the point ofmeasurement may be 1.2nsec but ......
asked by tom
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votes0
answers
DDR2 problem
Having some issues with a 225MHz DDR2 implementation at high temperature.I am wondering if the probl......
asked by bryan lastest answer by Hermann.Ruckerbauer
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answers