The JEDEC Solid State Technology Association, formerly known as the Joint Electron Device Engineering Council (JEDEC), is an independent semiconductor engineering trade organization and standardizatio

learn more…

source of DDR 4 timing recommendations


Can anyone help me understand the source of the pcb routing recommendationsI see for DDR4. For inst......

asked by ericsilist lastest answer by Nitin_Bhagwath

6 years 5 months 24 days

0

votes

6

answers
2682 views

wirebond inductance and bonding machine parameter......


Hi folksin our Power Amplifier application we almost use Au wirebond together withchip capacitor (IP......

asked by cristian.gozzi

6 years 6 months 24 days

0

votes

0

answers
2025 views

DDR4 Logic Level


Hi Experts,It seems that input logic level VIH(AC)&VIH(DC)&VIL(DC)&VIL(AC) are not given out in the ......

asked by icermail

7 years 1 month

0

votes

0

answers
2001 views

DDR3 Slew Rate Measurement


Hi,I am currently measuring slew rate of DDR3 (MT41J128M16JT-125IT; 1.5V) ADDRESS/Control signals. M......

asked by Nikhil.Ghode

7 years 3 months 11 days

0

votes

0

answers
2061 views

Measurement point for DDR3


Hi experts,I am validating pre-silicon an embedded DDR3 interface with simulation. The system is an ......

asked by ted.clark lastest answer by yousufs432

7 years 4 months 2 days

0

votes

10

answers
2503 views

DDR3 routing Topology selection


HiWe are designing a custom board where 2 DDR3 chips (533MHz) are interfacedwith processor. There ar......

asked by sonu.goyal lastest answer by hanymhfahmy

7 years 7 months 12 days

0

votes

10

answers
3436 views

DDR3 derate


Hi experts,Some Register of RDIMM compliance to JEDEC spec and there is no derating information in t......

asked by lijun_hit

7 years 8 months 23 days

0

votes

0

answers
1892 views

DDR3 read bit-deskew training mechanism


hi, Hermann & members,i am reading some vendor DDR3 IP spec. At DDR data training section, ican't u......

asked by zheng.jackle lastest answer by weirsi

8 years 2 months 20 days

0

votes

2

answers
2166 views

Check LPDDR2 CK-DQS timing


Hi, I'm going through LPDDR2 spec for CK-DQS timing definition on DRAM side. The spec has define......

asked by zlqin80 lastest answer by Hermann.Ruckerbauer

8 years 4 months 16 days

0

votes

3

answers
2817 views

LPDRR3 spec questions


Hi Experts,I have a few questions on LPDDR3 JEDEC spec (Please refer to the attacheddoc)Pg 100: Tabl......

asked by r.harianand

8 years 4 months 8 days

0

votes

0

answers
2184 views

Job Posting for SI Engineer


Micron Technology, Inc. has an opening for an experienced SI Engineer.You can contact me directly or......

asked by rkrichards lastest answer by testjo55

8 years 6 months 18 days

0

votes

1

answers
1911 views

DDR3 HSPICE Simulation


Hello, I have created a simple HSPICE deck to do the following. can someone letme know is there any ......

asked by signal.integrity2

8 years 8 months 19 days

0

votes

0

answers
1759 views

DDR3 1600 slew rate


Hi, All :    I am confused when reading the derating table of DDR3 1600. In Jedec, the derating valu......

asked by jessica_wuluan lastest answer by hermann.ruckerbauer

8 years 8 months

0

votes

3

answers
2269 views

DDR3 CK/CK# termination


Hi, I was looking at the JEDEC spec for DDR3 DIMMs and saw that the termination for the CK/CK# is th......

asked by snehamay lastest answer by tom

9 years 5 days

0

votes

2

answers
1859 views

Opportunity at Intel India| Signal Integrity


HiMy name is Priyanka & I work for the Staffing team at Intel India. Currently we have positions ope......

asked by priyankax.g.sharma

9 years 10 months 26 days

0

votes

0

answers
1731 views

DDR3 tQH spec.


Hello all,I'm looking for some background on the development of the JEDEC requirement for tQH (outpu......

asked by John.Ellis lastest answer by John.Ellis

9 years 12 months 16 days

0

votes

3

answers
1863 views

HCSL


Ray Anderson had asked this question back in 2005, though I saw no reply.Is there some kind of offic......

asked by tnbiggs lastest answer by ray.anderson

10 years 4 months 6 days

0

votes

3

answers
1759 views

Input spec difference between LVCMOS & SSTL


Hi Everyone Does anyone know why there is AC and DC VIH/VIL spec for SSTL & HSTL input but there is ......

asked by yshour2001 lastest answer by yshour2001

10 years 6 months 27 days

0

votes

4

answers
2336 views

JEDEC Complaince tests


Hi All,We are using the 3rd party memory controller along with their PHy with DDR2devices.Should we ......

asked by sudarshankr lastest answer by weirsi

10 years 8 months 12 days

0

votes

3

answers
1595 views

unbalanced setup/hold for DDR3 read


Hi,I made a small spreadsheet to help my understanding on DDR3 read timing for DQ/DQs. Data are extr......

asked by perry.qu lastest answer by buenos

10 years 9 months 3 days

0

votes

4

answers
1765 views
Looking for more? Browse the complete list of questions, or popular tags. Help us answer unanswered questions.