Ground bounce is one of the primary causes of glitches and spurious transitions in high-speed logic and can cause significant signal degradation between logic devices. This effect is most pronounced a

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Do SERDES interfaces need Power Aware SI channel ......


*Hi Team,*Could anybody let me know the importance of Power Aware simulation in todayHigh Speed appl......

asked by rameshp3note lastest answer by chris.cheng

5 years 15 days

0

votes

2

answers
2493 views

Power Aware IBIS and Separate VCCPD (predrive) sup......


Experts,I am looking to use IBIS 5.x for some SSO simulations. However, my die and package have an ......

asked by kowal_edward2007

5 years 5 months 22 days

0

votes

0

answers
2126 views

bit inversion in DDR3


Hello experts.DDR4 has got new feature of bit-inversion to control SSN jitteris it possible to imple......

asked by dmarc-noreply lastest answer by Hermann.Ruckerbauer

5 years 11 months 24 days

0

votes

1

answers
2024 views

How to get worst case in SSN analysis


Hi experts,When doing SSN analysis for DDR interface, I would like to get the worst case to check th......

asked by icermail lastest answer by orphanou

7 years 5 months 7 days

0

votes

2

answers
1591 views

SSN Worst case Analysis


Hi experts,When do SSN analysis, how can I capture the worst case? What I know is PVT & binary seque......

asked by icermail

7 years 5 months 9 days

0

votes

0

answers
1675 views

equal length requirement for SDRAM signals


hi, experts,in many vendors' SDRAM layout guide line, there is equal length requirement for SDRAM gr......

asked by aleilee lastest answer by Hermann.Ruckerbauer

7 years 8 months 9 days

0

votes

4

answers
1649 views

Modelling SSN noise


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asked by jasonwuc

7 years 8 months 4 days

0

votes

0

answers
1617 views

Modeling SSN Noise


ée KÞ¯&èw/Èjjî?x§«kj{"z{\?©çz["?éZ¶*'~?ÚuÚâ?׫}§Â«x?Z½è(µ«¥ªÚµëÿ¥ªÚ?ë^­ø¥zÇè®?0z·^?+Þ¯)Þ·+?óÃ7ö......

asked by jasonwuc

7 years 8 months 4 days

0

votes

0

answers
1573 views

SI Lab Lead at Xilinx


My team is looking for a senior SI Lab Lead to drive our SI lab activities. Please contact me at yon......

asked by yong.wang

7 years 12 months 7 days

0

votes

0

answers
1772 views

Does the signal reference to the vddq will increa......


Hi all: this question maybe......

asked by liewluping lastest answer by Peng_Shao

7 years 12 months 8 days

0

votes

11

answers
1755 views

DDR3 1600 slew rate


Hi, All :    I am confused when reading the derating table of DDR3 1600. In Jedec, the derating valu......

asked by jessica_wuluan lastest answer by hermann.ruckerbauer

8 years 4 months 29 days

0

votes

3

answers
2116 views

Job Opportunity at Altera


req #1915As a Signal Integrity Architect, you will oversee the design, development and validation of......

asked by msarmien

8 years 10 months 5 days

0

votes

0

answers
1568 views

Chip capacitance effect for SSN simulation - ANOT......


Hi folksI'm sorry to bother you again on this topicduring some email exchange, I had some feedback r......

asked by cristian.gozzi lastest answer by weirsi

8 years 11 months 18 days

0

votes

1

answers
1917 views

Which Return plane....


Hello All,I am new to Cadence PCB SI,I have a question, in PCB SI if a signal is passing thru Multip......

asked by makkan2001 lastest answer by weirsi

8 years 11 months 23 days

0

votes

1

answers
1543 views

Chip capacitance effect for SSN simulation


Hi SI membersI'm simulating DDR2 SSN for a Probe Card systemfor those that are not familiar with thi......

asked by cristian.gozzi lastest answer by weirsi

8 years 11 months 23 days

0

votes

7

answers
1813 views

signal integrity engineer opening at Altera


Hi all,My group has an signal integrity engineer opening. Below is the job description. You can send......

asked by ssun

9 years 2 months 12 days

0

votes

0

answers
1773 views

Regarding SSN


Hi All,I need to do SSN and ESD analysis. For the same If anyone can share thebasic presentations re......

SSN

asked by paramjeet.singh.79 lastest answer by rajeshk0212

9 years 3 months 10 days

0

votes

1

answers
1545 views

Does power/ground pair edege radiation noise real......


Dear all: The PDN noise voltages at the edges of a PCB are potential electromagnetic interferenc......

asked by liuluping lastest answer by xushuai

9 years 9 months 20 days

0

votes

15

answers
1861 views

design of on-chip PDN


Hi All, I have a basic question related to on-chip PDN design. Usually the supplyvoltages are desi......

asked by pansiming86 lastest answer by weirsi

9 years 10 months 12 days

0

votes

10

answers
2061 views

Sigrity webcast for frequency domain SSN analysis


Sigrity will be hosting a webcast focused on identifying simultaneousswitching noise (SSN) issues wi......

asked by wwang

9 years 11 months 16 days

0

votes

0

answers
1454 views
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