In electronics, overshoot refers to the transitory values of any parameter that exceeds its final (steady state) value during its transition from one value to another. When they are lower than the fin

learn more…

Reg:Overshoot and undershoot levels for 100mbps M......


Hi Team,In our design i am using One Ethernet PHY supporting 10/100 Mbps speed.I amcarrying out Sign......

asked by gkravi.1988 lastest answer by rajivra20

5 years 7 months 24 days

0

votes

3

answers
2441 views

termination on cpci


Hello expert.Reading document PICMG 2.0 R3.0 (Oct 1999), I see Compact PCI "standard" assumes many b......

asked by pietrov lastest answer by weirsi

6 years 10 months

0

votes

2

answers
2391 views

DDR3- Undershoot Area and Vss


/ÈýÙb?ëh?z0}ì-?)à²Úzj+zÊ^r'âs­?0ÑÝ*^sýÿ?l²ö¥¹ì"?[Ú¯&Ú±çhW?±æÞ??Þ²???ø?iº.µYìýhZ¶+þ{&y©ì?êÞÿö§u......

asked by sriram lastest answer by sriram

6 years 12 months

0

votes

4

answers
1898 views

DDR3 routing Topology selection


HiWe are designing a custom board where 2 DDR3 chips (533MHz) are interfacedwith processor. There ar......

asked by sonu.goyal lastest answer by hanymhfahmy

7 years 7 months 12 days

0

votes

10

answers
3436 views

Re: DC threshold multicross, undershoot and overs......


Hi I am new to SI field. Could you please explain with details how the DC threshold multicross, Unde......

asked by balajy.kumar

8 years 1 month 12 days

0

votes

0

answers
1943 views

what level of overshoot is acceptalbe


Hi guys, I have a problem: what level of overshoot is acceptable? I wasordered to qualify a ......

asked by Zhenwei.Wang lastest answer by kundro85

9 years 1 month 8 days

0

votes

5

answers
2171 views

Re: [SI-LIST] Re: 答复: [SI-LIST] Crosstalk and Ove......


The polarityof the FEXT is related with the capacitive & inductive coupling. If the inductive coupli......

asked by bh96048 lastest answer by pugal8686

9 years 6 months 11 days

0

votes

1

answers
1998 views

答复: [SI-LIST] Re: [SI-LIST] Re: 答复: [SI-LIST] Cro......


Pugal,Basically, yes. The simulation tools can tell you the overall corsstalk and reflections.But by......

asked by Peng_Shao

9 years 6 months 11 days

0

votes

0

answers
2011 views

答复: [SI-LIST] Crosstalk and Overshoot/Undershoot


Well, Pugal, one thing should be clear.Nobody says that " the values of far end crosstalk will be ne......

asked by Peng_Shao lastest answer by scott

9 years 6 months 12 days

0

votes

1

answers
2177 views

Crosstalk and Overshoot/Undershoot


Hi,The crosstalk theory says that the values of  far end crosstalk will be negative and near end cro......

asked by pugal8686 lastest answer by weirsi

9 years 6 months 12 days

0

votes

2

answers
1929 views

Ringing in Lumped & Distributed Circuits


Hello Experts,I have a problem understanding ringing concept in lumped and distributedcircuits. What......

asked by all.si.list lastest answer by Gert.Havermann

9 years 8 months 26 days

0

votes

9

answers
2369 views

Doubt about DDR1 memory module's CLK topology


Hi, SI experts.   I have some questions about DDR1 memory module's clock topology.   There are three......

asked by venussoso lastest answer by weirsi

10 years 4 months 20 days

0

votes

3

answers
2090 views

Undershoot/Overshoot Violations


We've been having some local discussions/debates on which specs should be used for evaluating unders......

asked by herse lastest answer by dburns

10 years 8 months 7 days

0

votes

4

answers
2185 views

Draft IBIS 5.0 specification now available for re......


The IBIS Open Forum is pleased to announce the availability of a reviewdraft of the IBIS 5.0 specifi......

asked by michael.mirmak

12 years 6 months 6 days

0

votes

0

answers
1710 views

LVCMOS to HSTL


Hi All,I'm looking at a 1.5V HSTL RGMII interface between a Xilinx Virtex5 FPGAand a processor, spec......

asked by SSantangelo

12 years 6 months 10 days

0

votes

0

answers
1669 views

Overshoot/undershoot for IO buffer


Hi,I began to suspect something I did before wasn't right. For a simpletopology of a driver and seve......

asked by shawn.h.zheng lastest answer by weirsi

13 years 1 month 28 days

0

votes

5

answers
1839 views

Free SI training in Beijing China by IO Methodolo......


This is a free training information email, please just ignore this unlessyou feel it useful. Thanks.......

asked by xjzhang

13 years 5 months 8 days

0

votes

0

answers
1873 views

Undershoot issues


=20Hi,I am observing undershoot alone in my simulation and also in some of theon-borad captures of s......

asked by vani.chandrasekharan lastest answer by jory_mckinley

13 years 5 months 10 days

0

votes

13

answers
1634 views

overshoot and undershoot different swing


Hi all,We are having 76 MHZ clock output from FPGA in our design.I am seeing on oscilloscope that th......

asked by rajeev.kommera lastest answer by janton

13 years 9 months 1 day

0

votes

5

answers
1661 views

MPX bus impedance


I'm looking at an MPX bus implementation with a single PowerPC and aXilinx FPGA. The bus is curren......

asked by SSantangelo

13 years 10 months

0

votes

0

answers
1593 views
1 2
Looking for more? Browse the complete list of questions, or popular tags. Help us answer unanswered questions.