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Wiring Harnessing SI Question


HI all --Hoping that list can shed some light on some wire harness related SIquestions at some very,......

asked by movax lastest answer by corley

4 years 10 months 22 days

0

votes

4

answers
3142 views

Re: Oscilloscope bandwidth and Non-Monotonic


BalaThe clock may toggle at 125 MHz and the edge rate at the point ofmeasurement may be 1.2nsec but ......

asked by tom

5 years 10 months 2 days

0

votes

0

answers
1789 views

options for reducing EMI


Hi SI Gurus,We are considering the following options in order to reduce the EMI of one of our boards......

asked by sherman.chen lastest answer by weirsi

6 years 21 days

0

votes

16

answers
1915 views

crosstalk and pcb placement of buses on high dens......


How does one decide which interfaces to route next to one another on a tighlty spaced pcb if xtalk i......

asked by bernadineps lastest answer by rod

8 years 9 months 6 days

0

votes

1

answers
1542 views

Digital F-mux


Has anybody here ever attempted to multiplex very low edge rate OOB signals onto a doubly-AC-coupled......

asked by dpalmer lastest answer by weirsi

9 years 7 months 3 days

0

votes

5

answers
1706 views
10 years 3 months 15 days

0

votes

0

answers
1785 views

bandwidth: based on edge rate or data rate?


The debate over what "rule of thumb" to use with regard to modelingbandwidth has been going on befor......

asked by zabinski.patrick lastest answer by tom

10 years 6 months 10 days

0

votes

6

answers
1876 views

SAS2 and StatEye questions


Hello, experts, I am trying to run the SAS2 compliant channel simulation using StatEye.In SAS2 speci......

asked by adiu_panli

10 years 11 months 10 days

0

votes

0

answers
1761 views

Latching relays in optical switches


Hello, I know that this question strays from SI, but it involves EM, and that's something that we i......

asked by dhwn lastest answer by weirsi

11 years 4 months 3 days

0

votes

12

answers
1627 views

Split Reference Plane Madness


Hello All,First off, thanks for all the help pointing me to some SI tools earlier.I'm currently work......

asked by cmaryan lastest answer by scott

11 years 4 months 15 days

0

votes

1

answers
1406 views

Errata for "Timing Analysis for Signal Integrity ......


1. Page 17. On the second rising edge of the clock in Figure 2.3, the Q output should stay high.2. ......

asked by gedlund lastest answer by colin_warwick

11 years 6 months 24 days

0

votes

2

answers
1577 views

Information regarding Stackup Design.


Gurus,I would like to get your valuable feedback on the following:1) Advantages/Disadvantages about ......

asked by rgali lastest answer by Alexander.Ippich

12 years 2 months 16 days

0

votes

12

answers
1636 views

Matching differential traces


Hi All,My question is related to matching differential traces on PCB.What the theoretical explanatio......

asked by EdiFraiman lastest answer by leeritchey

13 years 4 months 16 days

0

votes

4

answers
1594 views

Transmission Line Causality


Hi, I would like to raise a discussion on testing causality of a frequency dependent lossy transmis......

asked by si.rules lastest answer by vladimir_dmitriev-zdorov

13 years 5 months 8 days

0

votes

5

answers
1622 views

How much plane under traces is required for provi......


HiWe are in the process of laying out a PCB, due to safety requirements we can not provide a full co......

asked by Erin.McPhalen lastest answer by syedmhusain

13 years 8 months 11 days

0

votes

2

answers
1608 views

Re: Stimulus for spice-to-IBIS


Hi, Liang,In fact, you can get correct IBIS with any kind of edge rate as corestimulus (be reasonab......

asked by helen.tao.xu

13 years 8 months 29 days

0

votes

0

answers
1534 views

Undershoot or Overshoot Issue at Die Level


Hello Si-List,I am using Cadence's SigXplorer and am fairly new at interpretingthe results of IBIS s......

asked by deanrfitzgerald lastest answer by Aubrey_Sparkman

14 years 3 months 17 days

0

votes

1

answers
1461 views

Signal Integrity issues at -40 degrees C


Hello,We are starting a new design with 5 DDR2 memory busses and threemicroprocessors. The design mu......

asked by jhill lastest answer by weirsi

14 years 4 months 19 days

0

votes

6

answers
1723 views

Effect of Pwr-Gnd plane pairing vs. non-paired pl......


Normally, when I design a multi layer stackup I always try to alternate and pair Pwr-Gnd planes to m......

asked by alexh1 lastest answer by vinu

14 years 7 months 21 days

0

votes

10

answers
1195 views

Maximum frequency consideration for high-speed di......


Hi Everyone,I'm designing a differential signal for the Rocket I/O interface. My signalspeed is 5 Gb......

asked by rula.bakleh

14 years 8 months 3 days

0

votes

0

answers
1403 views
1 23
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