specific to the GNU/Linux operating system. If your question has nothing to do with Linux APIs or Linux-specific behavior you should not use this tag, even if you
TDR Rise time
Hi,Can I get help in understanding TDR rise time calculation? I came across10% to 90% calculation an......
asked by gmanikandan20 lastest answer by richard.mellitz
0
votes
edge connector layout optimization
I'm designing 6Gbps interconnect using edge connector.i try to optimize it's layout using this flow1......
asked by qantrix
0
votes0
answers
NEXT vs. Frequency
Hello experts!It is well known that NEXT coefficient is dictated by the properties of theinterconnec......
0
votes6
answers
DVI compliance woes
I'm performing DVI compliance testing on a board with ptn3360d TMDS level shifters followed by WURTH......
0
votes1
answers
Calculating rise time from IBIS
Hi Experts,A basic question on calculating rise time from ISI -In the IBIS file, the ramp data for a......
asked by hitheshn lastest answer by ferhatyaldiz
0
votes12
answers
Oscilloscope bandwidth and Non_Monotonic
Hi All,I am measuring 125MHZ,1.2ns rise time clock with Tek's scope.When i measure clock with 5G Ban......
asked by balaseven lastest answer by goswamisurjendra
0
votes3
answers
ddr3 Vtt sso issue
In our test setup we measured a surge of up to 500mV on Vtt when all addresses switch (qty = 20) fr......
asked by dmarc-noreply lastest answer by paul.taddonio
0
votes5
answers
Clarification on Trace Routing over Plane Splits
Hi all -I have previously spent time in the high-speed realm, routing PCIe,SATA, HT, and many other ......
0
votes4
answers
Bandwidth Problem
Hi All,I am trying to decide a voltage translator IC and I have some questionsthat I believe I can g......
0
votes1
answers
TDR- rise time-channel bandwidth and speed
Seems the more you want to dig and clear the more confuse you will have.Some one tells me the more s......
0
votes4
answers
Signals crossing power plane splits
Hi all, We might have discussed about this subject here, but, I would like to getmore perspective o......
0
votes1
answers
Can I help?
Hello to the SI list.I am new to this list but not new to problems of board design. I have read m......
asked by ralphmorrisonee lastest answer by olaney
0
votes3
answers
Doubt about RC constant Low Pass Filter
Hi, Si-List friends,This is my first post. I do a very simple simulation in Hyperlynx about RClow pa......
asked by cnmuggle lastest answer by istvan.novak
0
votes3
answers
Regarding considering a transmission line as lump......
I am just elaborating my question.I have came across different formula's to say whether a Transmissi......
asked by malli.1729 lastest answer by Wolfgang.Maichen
0
votes6
answers
Eye width for microstrip and stripline configurat......
Dear experts,I am currently working on a PCIE gen2 simulation. I am evaluating both themicrostrip an......
0
votes5
answers
HSPICE help needed
> Each time I have to use HSPICE, I am reminded why it is NOT my favorite > tool.... :-( > > I ha......
asked by asparky
0
votes0
answers
layout of DSP driving 2 SDRAM
Hi ALL,I have some queries about SDRAM layout.One DSP drives two SDRAM,The clock frequency is 166MHz......
asked by LindaXinCai.Tang lastest answer by erdinih
0
votes4
answers
Rise/Fall time Vs Bit rate.
Experts,We all have read that in high speed design it's rise time that createssignal integrity issue......
asked by rajneeshs123 lastest answer by Gert.Havermann
0
votes17
answers
TDR questions
I am considering renting a TDR to characterize a SATA 6 GB/S signal pathincluding cables, connectors......
0
votes3
answers
Free Agilent High Speed Digital Seminars: UK (Win......
Hi si-listers,We're offering free full day technical seminar delivered Agilent experts in high speed......
asked by colin_warwick
19
answers