specific to the GNU/Linux operating system. If your question has nothing to do with Linux APIs or Linux-specific behavior you should not use this tag, even if you

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TDR Rise time


Hi,Can I get help in understanding TDR rise time calculation? I came across10% to 90% calculation an......

asked by gmanikandan20 lastest answer by richard.mellitz

4 years 7 months 13 days

0

votes

19

answers
3707 views

edge connector layout optimization


I'm designing 6Gbps interconnect using edge connector.i try to optimize it's layout using this flow1......

asked by qantrix

5 years 2 months 1 day

0

votes

0

answers
1818 views

NEXT vs. Frequency


Hello experts!It is well known that NEXT coefficient is dictated by the properties of theinterconnec......

asked by bbakshan lastest answer by jpoltz

5 years 4 months 2 days

0

votes

6

answers
2023 views

DVI compliance woes


I'm performing DVI compliance testing on a board with ptn3360d TMDS level shifters followed by WURTH......

asked by andrew lastest answer by tom

5 years 8 months 2 days

0

votes

1

answers
2332 views

Calculating rise time from IBIS


Hi Experts,A basic question on calculating rise time from ISI -In the IBIS file, the ramp data for a......

asked by hitheshn lastest answer by ferhatyaldiz

5 years 11 months 26 days

0

votes

12

answers
2242 views

Oscilloscope bandwidth and Non_Monotonic


Hi All,I am measuring 125MHZ,1.2ns rise time clock with Tek's scope.When i measure clock with 5G Ban......

asked by balaseven lastest answer by goswamisurjendra

5 years 11 months 2 days

0

votes

3

answers
2127 views

ddr3 Vtt sso issue


In our test setup we measured a surge of up to 500mV on Vtt when all addresses switch  (qty = 20) fr......

asked by dmarc-noreply lastest answer by paul.taddonio

6 years 4 months 12 days

0

votes

5

answers
2439 views

Clarification on Trace Routing over Plane Splits


Hi all -I have previously spent time in the high-speed realm, routing PCIe,SATA, HT, and many other ......

asked by movax lastest answer by movax

6 years 7 months 1 day

0

votes

4

answers
2619 views

Bandwidth Problem


Hi All,I am trying to decide a voltage translator IC and I have some questionsthat I believe I can g......

asked by soner86 lastest answer by weirsi

6 years 7 months 2 days

0

votes

1

answers
1839 views

TDR- rise time-channel bandwidth and speed


Seems the more you want to dig and clear the more confuse you will have.Some one tells me the more s......

asked by fuyejun lastest answer by tom

6 years 10 months 15 days

0

votes

4

answers
1928 views

Signals crossing power plane splits


Hi all, We might have discussed about this subject here, but, I would like to getmore perspective o......

asked by bala89si lastest answer by weirsi

6 years 11 months 13 days

0

votes

1

answers
1985 views

Can I help?


Hello to the SI list.I am new to this list but not new to problems of board design. I have read m......

asked by ralphmorrisonee lastest answer by olaney

7 years 27 days

0

votes

3

answers
2496 views

Doubt about RC constant Low Pass Filter


Hi, Si-List friends,This is my first post. I do a very simple simulation in Hyperlynx about RClow pa......

asked by cnmuggle lastest answer by istvan.novak

7 years 2 months 24 days

0

votes

3

answers
2075 views

Regarding considering a transmission line as lump......


I am just elaborating my question.I have came across different formula's to say whether a Transmissi......

asked by malli.1729 lastest answer by Wolfgang.Maichen

7 years 3 months 7 days

0

votes

6

answers
1727 views

Eye width for microstrip and stripline configurat......


Dear experts,I am currently working on a PCIE gen2 simulation. I am evaluating both themicrostrip an......

asked by maxsidhu lastest answer by al

7 years 8 months 9 days

0

votes

5

answers
2270 views

HSPICE help needed


> Each time I have to use HSPICE, I am reminded why it is NOT my favorite > tool.... :-( > > I ha......

asked by asparky

8 years 23 days

0

votes

0

answers
1739 views

layout of DSP driving 2 SDRAM


Hi ALL,I have some queries about SDRAM layout.One DSP drives two SDRAM,The clock frequency is 166MHz......

asked by LindaXinCai.Tang lastest answer by erdinih

8 years 1 month 22 days

0

votes

4

answers
1817 views

Rise/Fall time Vs Bit rate.


Experts,We all have read that in high speed design it's rise time that createssignal integrity issue......

asked by rajneeshs123 lastest answer by Gert.Havermann

8 years 1 month 6 days

0

votes

17

answers
1831 views

TDR questions


I am considering renting a TDR to characterize a SATA 6 GB/S signal pathincluding cables, connectors......

asked by joel lastest answer by tom

8 years 5 months 5 days

0

votes

3

answers
1993 views

Free Agilent High Speed Digital Seminars: UK (Win......


Hi si-listers,We're offering free full day technical seminar delivered Agilent experts in high speed......

asked by colin_warwick

8 years 6 months 23 days

0

votes

0

answers
1653 views
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