the difference in arrival time of simultaneously transmitted signals.

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Glass Weave effects and Cross sectioning


Hi experts,I've been reading much on glass weave effects and its contribution on skew.If I encounter......

asked by bbakshan lastest answer by istvan.novak

5 years 24 days

0

votes

49

answers
5326 views

Testing DVI Cables


Can someone point me to a company that can test DVI cables?I need to perform a TDR test for the foll......

asked by charles lastest answer by al

5 years 2 months 16 days

0

votes

1

answers
2314 views

Skew vs length matching


Hello guys,I am making a board using a FPGA whose serdes runs on 12.5 Gbps.Owing to the FPGA ball ma......

asked by amit.j.kumar lastest answer by jpnathan

5 years 8 months 13 days

0

votes

2

answers
2601 views

Vias in LPDDR2 traces


HiPlease can someone provide a little advice regarding vias in LPDDR2 traces?The issue concerns the ......

asked by jonathan.lloyd.riley lastest answer by Hermann.Ruckerbauer

5 years 11 months

0

votes

2

answers
2585 views

DDR3 DQ-DSQ skew over temperature


Dear all,In read leveling procedure DQS and DQ signals are aligned in the controllerso that optimum ......

asked by bbakshan lastest answer by Hermann.Ruckerbauer

6 years 18 days

0

votes

1

answers
2529 views

Glass-Weave Skew / Fiber-Weave Effect


Hi Folks …I’m doing a bit of research on glass-weave skew / the fiber-weave effect. I’ve read the a......

asked by billh

6 years 1 month 21 days

0

votes

0

answers
1941 views

DDR3 termination on address / control lines


In my design there are two DDR3 chips on the boards.Is it better to use a fly by termination or T wi......

asked by joel lastest answer by gnuarm.2006

6 years 9 months 8 days

0

votes

3

answers
2044 views

Regarding AC Input test conditions and Slew rate ......


When i am reading DDR2 specifications,i got 2 different definitions for input signal slew rate , one......

asked by malli.1729 lastest answer by ferhatyaldiz

7 years 1 month 23 days

0

votes

1

answers
2010 views

Differential signals - skew - and EMC


Hello,In an ideal situation differential signals will have no skew through the transmission path and......

asked by Charles.Grasso lastest answer by leeritchey

7 years 2 months

0

votes

11

answers
2074 views

Help implementing SET2DIL in Matlab


Hello all,I'm currently trying to measure differential insertion loss with SET2DIL. I've developed m......

asked by Michelle.Rybak lastest answer by jeff.loyer

7 years 2 months 1 day

0

votes

1

answers
2137 views

GND vs Power as reference


(I've changed the "Subject" title a bit...)I think that if I was "dead wrong", no one in the entire ......

asked by jeff.loyer lastest answer by shengli.lin.sl

7 years 3 months

0

votes

24

answers
2883 views
7 years 3 months

0

votes

0

answers
2594 views

DDR2-Vref Noise


HiIn ddr2, VREF noise causes strobe-to-data skew. Since DQ and DQS areconnected to same Vref, then h......

asked by kbmanick lastest answer by Hermann.Ruckerbauer

7 years 5 months 28 days

0

votes

3

answers
2027 views

Why is shield grounding necessary for Inpair Skew......


Hi, I am interested in in-pair skew. Hoping another expert could help! :) Does anyone know why groun......

asked by jsven006 lastest answer by weirsi

7 years 5 months 2 days

0

votes

3

answers
1643 views

write time budget for DDR2


HiI am calculating the Data write time budget for DDR2 interface.I referred the following document.h......

asked by kbmanick

7 years 6 months 10 days

0

votes

0

answers
2077 views

DDR2 length matching address and clock


Dear Experts,This is regarding the trace length matching between DDR2 address and clocksignals.*As p......

asked by kbmanick lastest answer by weirsi

7 years 8 months 14 days

0

votes

1

answers
2048 views

Dynamic phase compensation in SERDES layout


Hi, Experts,I'm very curious that why the dynamic phase compensation(DPC)/running skewcompensation i......

asked by xiaogcai lastest answer by xiaogcai

8 years 21 days

0

votes

5

answers
1825 views

DDR3 controller internal package delay Considerla......


Hi,Recently I have a case which is the DDR3 1600 layout consideration.I foundour DDR3 Controller ha......

asked by lipishang lastest answer by weirsi

8 years 1 month 4 days

0

votes

5

answers
1957 views

Resedn:Mitigating PCB fiber weave effect


Hi,Today read two two Designcon paper about PCB fiber weave effect1 The Impact of PCB Laminate Weave......

asked by emcesd lastest answer by weirsi

8 years 3 months 11 days

0

votes

9

answers
2130 views

Check LPDDR2 CK-DQS timing


Hi, I'm going through LPDDR2 spec for CK-DQS timing definition on DRAM side. The spec has define......

asked by zlqin80 lastest answer by Hermann.Ruckerbauer

8 years 4 months 19 days

0

votes

3

answers
2820 views
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