DDR3-1600 Double-Tee Topology

Hi Everyone,Has anyone tried using a double-tee topology with their address/command/control signals in DDR3L/LPDDR3?  This would be instead of the standard daisy-chain, with an Rtt at the end of the line.For example, take a controller with four memory nodes.  It would look like this (think of DDR2 days):                                          - RX                         - Branch -|                        |                  - RXTX ----------------- Rtt                        |                 - RX                         - Branch-|                                                                    - RXTo ensure matched timing for write leveling, this would even apply to the differential clock.  I am doing memory-down (chips directly on the PWB as opposed to DIMMs.. if that matters?) Compared to a simple daisy chain, my simulations show this to be a bad idea both in eye diagram margins and in s-parameter plots.  The double tee has less vertical / horizontal eye margin.  The double-tee also has a resonant "suck out" in insertion loss very close to the clock frequency, whereas the standard daisy-chain is relatively flat out to 3GHz.  Our chip vendor tells us this is needed to improve the eye diagram, but I can't see how or why.  This is also a pain to route.. and so I have no good ideas as to why I should do this :)Am I missing something?  Thoughts?  Anyone else in the same boat? :)Thank you,Joseph Aday
josephaday 6 years 10 months 22 days

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Answered byadayjoseph-lists 6 years 10 months 17 days
Hi Everyone,I get very good simulation results after making adjustments per Brian Moran's earlier emails.  The main trick seems to be working out producible trace widths such that the impedance of the branches can be compensated against the main route.  That being said, I agree with everyone that the daisy chain is still the best (easiest!) as long as it shows good margins.. and will only use the double-tee in the case where I really need it ;)  Thanks again everyone for so much great advice and excellent discussion.Joseph________________________________ From: Hermann Ruckerbauer To: Joseph Aday ; "Nikhil.Ghode@xxxxxxxxxxxxxx" ; "prashant.jaiswar@xxxxxxxxx" ; Surjendra Goswami ; "brian.p.moran@xxxxxxxxx"  Cc: "si-list@xxxxxxxxxxxxx"  Sent: Wednesday, January 15, 2014 11:59 AMSubject: [SI-LIST] Re: DDR3-1600 Double-Tee TopologyHello,I have done some analysis to check PowerUp behavior, but I have toadmit, that i never did a complete measurement of the delays that thediffent trainings will add.So far I had some systems that would care about microseconds delayduring runtime. But no system cared about some microseconds during Powerup. I think it is much more effort to characterize a system in order toset the parameter right vs. running the trainings ...I would spend the effort to save this time only if somebody can convinceme that the system cares about microseconds during boot. Guess this willnot be easy to convince me here   ;-)HermannAm 15.01.2014 19:32, schrieb Joseph Aday:> Hi Hermann,>> Thanks for adding that clarification.  Good point!>> I've wondered actually what boot-up savings I could get if I skipped> the write leveling from the boot-up.  Sometimes I'm fortunate enough> to work designs where I only need a chip or two and wouldn't need that> feature.  Hey all those microseconds add up right? :^)>> Joseph>> 
Answered byHermann.Ruckerbauer 6 years 10 months 20 days
Hello,I have done some analysis to check PowerUp behavior, but I have toadmit, that i never did a complete measurement of the delays that thediffent trainings will add.So far I had some systems that would care about microseconds delayduring runtime. But no system cared about some microseconds during Powerup. I think it is much more effort to characterize a system in order toset the parameter right vs. running the trainings ...I would spend the effort to save this time only if somebody can convinceme that the system cares about microseconds during boot. Guess this willnot be easy to convince me here   ;-)HermannAm 15.01.2014 19:32, schrieb Joseph Aday:> Hi Hermann,>> Thanks for adding that clarification.  Good point!>> I've wondered actually what boot-up savings I could get if I skipped> the write leveling from the boot-up.  Sometimes I'm fortunate enough> to work designs where I only need a chip or two and wouldn't need that> feature.  Hey all those microseconds add up right? :^)>> Joseph>> 
Answered byliviu-dumitru.craciun 6 years 10 months 20 days
The balanced-T topology is also possible and has the major advantage that it doesn`t need termination if the driver strength is proper defined.Normally needs the terminations a lot of PCB space and an extra power supply.Both, PCB space and the components of the power supply means extra costs.Best regards,Liviu Craciun==========================================-----Ursprüngliche Nachricht-----Von: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] Im Auftrag von Milnor StefanGesendet: Mittwoch, 15. Januar 2014 07:20An: adayjoseph-lists@xxxxxxxxx; mgreim001@xxxxxxxxxCc: si-list@xxxxxxxxxxxxxBetreff: [SI-LIST] Re: DDR3-1600 Double-Tee TopologyRegarding "who this vendor is" comment  - I don't know, but I have seen the Tee topology described for DDR3 use from two different Tier 1 SOC vendors that everyone has heard of.For one of the vendors, the application notes show the Tee topology and nothing else. Perhaps their part or software does not support the wear leveling that the daisy chain routing requires.The other vendor described both the daisy chain and tee topologies, with an emphasis on the daisy chain. The tee was offered for certain memory - down configurations.-----
Answered byadayjoseph-lists 6 years 10 months 20 days
Hi Hermann,Thanks for adding that clarification.  Good point!I've wondered actually what boot-up savings I could get if I skipped the write leveling from the boot-up.  Sometimes I'm fortunate enough to work designs where I only need a chip or two and wouldn't need that feature.  Hey all those microseconds add up right? :^)Joseph________________________________ From: Hermann Ruckerbauer To: Nikhil.Ghode@xxxxxxxxxxxxxx; "prashant.jaiswar@xxxxxxxxx" ; Surjendra Goswami ; "brian.p.moran@xxxxxxxxx"  Cc: "josephaday@xxxxxxxxx" ; "si-list@xxxxxxxxxxxxx"  Sent: Wednesday, January 15, 2014 12:38 AMSubject: Re: [SI-LIST] Re: DDR3-1600 Double-Tee TopologyHello,I think there have been already several comments on the topic T vs.flyby itself, so I'm not adding some more on this one.But one short comment on Write Leveling:It is not that you have to use fly-by because write leveling is afeature of DDR3, but you have to use Writeleveling in oder to allowfly-by routing.There is not reason not to use the Write-leveling training also for aT-Topology in order to optimize the Write DQS to CLK timing. With thisyou can adjust slight differences in CA timings (that should be anyhowsmall in the T config) but also avoid that you have to take care on theDQS to clock delay manually.In some of the previous mails it sounded different like: you have to useflyby because of WriteLeveling....HermannOur next Events:===============Embedded World 2014Visit our Boot in Hall 1 - Booth 602Follow our Presentation on the Conference:"Jitter in PCIe application on embedded boards with PLL Zero delay Clock buffer"This year first time with a Signal Integrity track on Thursday afternoon:http://www.embedded-world.eu/program.htmlCheck our website or contact us for detailsEKH - EyeKnowHowHermann Ruckerbauerwww.EyeKnowHow.deHermann.Ruckerbauer@xxxxxxxxxxxxxItzlinger Strasse 21a94469 DeggendorfTel.:    +49 (0)991 / 29 69 29 05Mobile:    +49 (0)176  / 787 787 77Fax:    +49 (0)3212 / 121 9008schrieb Ghode, Nikhil:> Joseph,> I recently used T-topology for DDR3 routing, however I used only two memories > running at 400MHz clock. Hence I had plenty of timing margin.> If you planning to use T-topology then I would not recommend to use write > leveling. It is useful in flyby to compensate for delays.>> It is important to check timing budget. Also check if you have enabled > terminations inside the DDR3 for write operation, you can also use dynamic > termination for write cycles.>> Regards,>> -Nikhil> Ph: 845-731-2277> Fax:845-731-2011>> -----
Answered byHermann.Ruckerbauer 6 years 10 months 20 days
Hello,I think there have been already several comments on the topic T vs.flyby itself, so I'm not adding some more on this one.But one short comment on Write Leveling:It is not that you have to use fly-by because write leveling is afeature of DDR3, but you have to use Writeleveling in oder to allowfly-by routing.There is not reason not to use the Write-leveling training also for aT-Topology in order to optimize the Write DQS to CLK timing. With thisyou can adjust slight differences in CA timings (that should be anyhowsmall in the T config) but also avoid that you have to take care on theDQS to clock delay manually.In some of the previous mails it sounded different like: you have to useflyby because of WriteLeveling....HermannOur next Events:================Embedded World 2014Visit our Boot in Hall 1 - Booth 602Follow our Presentation on the Conference:"Jitter in PCIe application on embedded boards with PLL Zero delay Clock buffer"This year first time with a Signal Integrity track on Thursday afternoon:http://www.embedded-world.eu/program.htmlCheck our website or contact us for detailsEKH - EyeKnowHowHermann Ruckerbauerwww.EyeKnowHow.deHermann.Ruckerbauer@xxxxxxxxxxxxxItzlinger Strasse 21a94469 DeggendorfTel.:   +49 (0)991 / 29 69 29 05Mobile: +49 (0)176  / 787 787 77Fax:    +49 (0)3212 / 121 9008schrieb Ghode, Nikhil:> Joseph,> I recently used T-topology for DDR3 routing, however I used only two memories > running at 400MHz clock. Hence I had plenty of timing margin.> If you planning to use T-topology then I would not recommend to use write > leveling. It is useful in flyby to compensate for delays.>> It is important to check timing budget. Also check if you have enabled > terminations inside the DDR3 for write operation, you can also use dynamic > termination for write cycles.>> Regards,>> -Nikhil> Ph: 845-731-2277> Fax:845-731-2011>> -----
Answered bystefan.milnor 6 years 10 months 20 days
Regarding "who this vendor is" comment  - I don't know, but I have seen the Tee topology described for DDR3 use from two different Tier 1 SOC vendors that everyone has heard of.For one of the vendors, the application notes show the Tee topology and nothing else. Perhaps their part or software does not support the wear leveling that the daisy chain routing requires.The other vendor described both the daisy chain and tee topologies, with an emphasis on the daisy chain. The tee was offered for certain memory - down configurations.-----
Answered bygoswamisurjendra 6 years 10 months 20 days
Joseph,DDR3 supports write leveling  and hence the fly-by topology is the mostprolific an DDR3 designs.The double tee topology was used for DDR2 and had some downside in theimpedance discontinuities due to branching along the routes causing obviousmargin losses.RegardsSurjendraOn Tue, Jan 14, 2014 at 10:25 PM, Moran, Brian P wrote:> Joseph,>> I have seen the Tee-Tee or the hybrid Tee-Daisy topology used in some> instances.  You are correct that the> Tee-Tee is a pain to route and usually requires a type 4 MB.  We do employ> it in some LPDDR3 memory down> configurations.  In either case, it does require some impedance> compensation between the main trunk and> the tee branches in order to optimize.  This is different than the tree> topology used in DDR2, in that the length> to all loads is matched.  Where we found the Tee-Tee particularly> interesting is when using multi-die pkgs.  The> daisy chain topology does not work well with high capacitance loads, such> as you can have with LPDDR3 DDP> and QDP devices.  You can get excessive ledging and ringback in the first> few nodes in the daisy chain. This is> the reason the Tee-Tee topology was developed.  However, if you are> supporting only SDP> devices then the daisy chain is the most straightforward.>> Brian Moran> Memory Interface Technology> Client Platforms> Intel Corporation>> -----
Answered byadayjoseph-lists 6 years 10 months 21 days
LOL!  Thanks Michael________________________________ From: Michael Greim To: josephaday@xxxxxxxxx Cc: "si-list@xxxxxxxxxxxxx"  Sent: Tuesday, January 14, 2014 9:26 AMSubject: [SI-LIST] Re: DDR3-1600 Double-Tee TopologyLove to know who this vendor is.....;-)going from DDR2 to DDR3 folks went fly by for a reason.  I recommend makingthem prove why ITHO a tree structure offers more margin than the fly by.Micron has some great papers on point to point design on chip downimplementations.   See if that offers any clarity.Otherwise, I would recommend running sims both ways and showing why nondouble T is the way to go.  Trust but always verify.Just my 0.02.   Rambus way back when said I could do short or long channeldesign and nothing else.  They were wrong too, but then again I can be a SIrebel at times.....;-)-Michael.We will either find a way or make one   - HannibalIn the middle of every difficulty lies opportunity   - Al EinsteinIf you think you can do something or you thinkyou can't, in both cases you are probably right   - H FordAnd if I claim to be a wise man it surely means I'm paid too much......;-)On Mon, Jan 13, 2014 at 8:06 PM, Joseph Aday  wrote:> Hi Everyone,>> Has>  anyone tried using a double-tee topology with their> address/command/control signals in DDR3L/LPDDR3?  This would be instead of> the standard daisy-chain,> with an Rtt at the end of the line.>> For example, take a controller with four memory nodes.  It would look like> this (think of DDR2 days):>>                                           - RX>                          - Branch -|>                         |                  - RX> TX ----------------- Rtt>                         |                 - RX>                          - Branch-|>                                           - RX>> To ensure matched timing for write leveling, this would even apply to the> differential clock.  I am doing memory-down (chips directly on the> PWB as opposed to DIMMs.. if that matters?)>> Compared>  to a simple daisy chain, my simulations show this to be a bad idea both>  in eye diagram margins and in s-parameter plots.  The double tee has> less vertical / horizontal eye margin.  The double-tee also has a> resonant "suck out" in insertion loss very close to the clock frequency,>  whereas the standard daisy-chain is relatively flat out to 3GHz.>> Our>  chip vendor tells us this is needed to improve the eye diagram, but I> can't see how or why.  This is also a pain to route.. and so I have no> good ideas as to why I should do this :)>> Am I missing something?  Thoughts?  Anyone else in the same boat? :)>> Thank you,> Joseph Aday> 
Answered byadayjoseph-lists 6 years 10 months 21 days
Hi Brian, all,Thank you for your responses and insight.  I did simulate both single and dual die configurations with DDR3L.  In my dual die configuration, the double tee looked even worse.  However, I did not make any effort to adjust the impedances through the tee- I will try that.  I'm not sure what you meant by it being different from DDR2 in that the lengths are matched (I thought they were?)  Is this a situation particular to certain controllers?  Would Intel be able to share data with me?  I do have both NDAs and PIAs in place.  Though I guess, in the end, I really need to see something positive in my own simulations ;)  Anyway, I will most likely go with a single die configuration and am thrilled to hear I can use a simple daisy chain for that. Thanks again,Joseph________________________________ From: "Moran, Brian P" To: "josephaday@xxxxxxxxx" ; "si-list@xxxxxxxxxxxxx"  Sent: Tuesday, January 14, 2014 9:55 AMSubject: [SI-LIST] Re: DDR3-1600 Double-Tee TopologyJoseph,I have seen the Tee-Tee or the hybrid Tee-Daisy topology used in some instances.  You are correct that theTee-Tee is a pain to route and usually requires a type 4 MB.  We do employ it in some LPDDR3 memory downconfigurations.  In either case, it does require some impedance compensation between the main trunk andthe tee branches in order to optimize.  This is different than the tree topology used in DDR2, in that the lengthto all loads is matched.  Where we found the Tee-Tee particularly interesting is when using multi-die pkgs.  Thedaisy chain topology does not work well with high capacitance loads, such as you can have with LPDDR3 DDPand QDP devices.  You can get excessive ledging and ringback in the first few nodes in the daisy chain. This isthe reason the Tee-Tee topology was developed.  However, if you are supporting only SDPdevices then the daisy chain is the most straightforward. Brian MoranMemory Interface TechnologyClient PlatformsIntel Corporation-----
Answered byhanymhfahmy 6 years 10 months 21 days
Yep long time dear Bowen.The output slew rate is very fast so w DDP, it actually smoothed out therising n falling creating nice eyes. W SDP, there is very strong ringbackdue to fast slew rate that we csn make it working only when we add cterm byHaswell pins. We don't have full control of output slew rate, that's why wehad to add Cterm like those old days , remember :)On Jan 14, 2014 7:44 PM, "Liu, Bowen"  wrote:>  It?s nice to hear from you too, Fahmy.  J>> It is strange to see failure with SDP, but passing with DDP with Haswell.>  It normally should be the other way around, as DDP has more loading which> gives worse margin in general.>>>> Thanks,>> Bowen>> *From:* Hany Fahmy [mailto:hanymhfahmy@xxxxxxxxxxxxxxxxxxx]> *Sent:* Tuesday, January 14, 2014 10:33 AM> *To:* Liu, Bowen; goswamisurjendra@xxxxxxxxx; Moran, Brian P> *Cc:* josephaday@xxxxxxxxx; si-list@xxxxxxxxxxxxx> *Subject:* RE: [SI-LIST] Re: DDR3-1600 Double-Tee Topology>>>> Hi Bowen. Long time man. We had a Recent case of a Haswell controller w> memory down failing w SDP but passing w DDP using daisy chain. My point is> that we can't generalize it n as u said u must simulate it especially for> memory down cases.>>>> I think indeed the conclusion is : it must be simulated n as we onow it is> also very sensitive to drver strength n output slew rate as well.>>>>>> Hany Fahmy>> CEO and Chief Consultant Officer>> Intelligent Solutions BVBA>> Http://www.intelligentsolutionsbvba.com>> +32471650724>> Sent from Samsung Mobile>>>>> -------- Original message --------> From: "Liu, Bowen" > Date:> To: goswamisurjendra@xxxxxxxxx,"Moran, Brian P" > Cc: josephaday@xxxxxxxxx,si-list@xxxxxxxxxxxxx> Subject: [SI-LIST] Re: DDR3-1600 Double-Tee Topology>>> Joseph,> It depends on whether you are designing a system with SDP (single die> package) or DDP (dual die package) DRAM devices.  If it is SDP, it doesn't> matter which topology you use, both daisy-chain and double-T topologies> should work fine for you, but if you are using DDP device, then double-T> topology works better than daisy-chain in term of giving better system> margin.  Even though daisy-chain topology (common for DDR3) can distribute> load effect to improve margin, but it normally can cause some reflections> among loads, and it is worse for DDP case.  I believe that's why DDR3/L> RC-D (daisy-chain with DDP device) was only supported up to 1066MTs.  Like> other people suggested, you can always run some simulation to verify which> topology works better for you when you have doubts like this.>> Thanks,> Bowen> -----
Answered byhanymhfahmy 6 years 10 months 21 days
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Answered byNikhil.Ghode 6 years 10 months 21 days
Joseph,I recently used T-topology for DDR3 routing, however I used only two memories running at 400MHz clock. Hence I had plenty of timing margin.If you planning to use T-topology then I would not recommend to use write leveling. It is useful in flyby to compensate for delays.It is important to check timing budget. Also check if you have enabled terminations inside the DDR3 for write operation, you can also use dynamic termination for write cycles.Regards,-NikhilPh: 845-731-2277Fax:845-731-2011-----
Answered bybowen.liu 6 years 10 months 21 days
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Answered byhanymhfahmy 6 years 10 months 21 days
N§?Àk?©ß¢»ayìi?©Ú¶*'ÿÿÇ£¯z¿ì¶)eÁç?f¤zØ^¶»?u¨¬Ë+?ëÞ?   Z®¢??­qªZr+ZÇ¨|0Ïo(§r[?xµêæjÛayÊ'¶º%?êé?{¢¶Þ¶×«?j^u©Üzf­r§??Þ½éÚuا?Ç«?ë+zÈ­¢»h¶??»-±ÚÚ?zzÚ&j×!¶¢??jwü.?z0jgÚ??í®çj+2ÿÿÇj|?j²C?Ð¡?ç¢{.?Ö§´çß?Ç«"{^?X z{R¢[­??ìP@ÛiÿÿðÃâ?×¥?(?Û(?ëb¢{½¶ÿr?¾ßn;×®tïnz{_®??jk.?(n)^ÿÿÿÿÿÿÿó«?§jY?²Æ{ÿÿÿÿÿüZè?ÿÌ¢¶§üâjsÿýºâjéþj+jâ?×¥ýÊ&ü6­{ôèþ:,z?Zu¬ÿɨh£÷(?û"þX¬·÷ëyéb²Ûÿ¢¸¹¸ÞrßÿHË!$ÿEïÃÿ×­4???ïÓyäè¦?h?"h±êaü?Z½ëz{ay7?ý7?¢»az?®'SyïÃj+2¶?h??2ºÇ?{(?觲֧qëÿÿö(¹ªÞr?ëyËm?«m?äÞ{ôÞz+¥¨§¶?èº×?Û¬¹©eÊ·ªº*Þ±«r¥îÿÿYçhzje£(­?{(?âÏ4w?騯'hÂw(ø º¶­??ìÿÿȝè­?êÜjÇÿ?×hzÊÞªè«zÊ&z)©yÖ§qç(??§±«b¢vÞ·??Ø^?¨§¶»§?©Ý¶­yæëjw!zȧ¢·^®Ú(¦Ø¦?7ÿÿôá?Ȭv'ßz·§¶ØZ?Ø^¶·?¶?h??2ºÇ?pÃGoâ?ØZ¶Ø^?éà¶hjYe¡§l?É?µÈ^wÿÿZ«{?¢éݶ?yïÓyêZ®Ø?ºV«?(§µê޲ا?+0?éî²)à?ém?÷bz? ³ÿÿNj+2r¢?Ú)¢Z ÉÚ²z-Â?äÁéeÂ+a?(!qªZr+ZÇ¥¡§lþË??«2¢ç?¯{­?³ÃÃö§u'?$?=ׯ?Ǭ¶§¶j+2r¢?+-?騲Û-­¨ ?×诫wðk?©Ì¢¶§1騯"'µêßiÇ?yÈg¢Z È)bz{O?«_¢¹¬"{^?*+¦?Ú¶*'ÿÿÿüêâ?)Ú?Ǭ±¨ÿÿÿüZè?û"þX¬·öèºwýúÞzX¬¶Ïè®æj)m£û"þX¬·öèºwýúÞzX¬¶Ïè®Î?¡jWÎ|?,z?@u¬?z{ÿ2?Ýk/Éj{?¯-wÿm5ã¯ôìó£û"þX¬·÷ëyéb²Ûÿ¢¸¹¸ÞrßÿHË!$ÿ4wÿ^´Ð:.nWÿMç?¢?%¢??KÞ¯*'{ñÚ±©ò¢w­®'ºÈ§§h¹¹^þ×?¶?h??2Â+a¶¢­§]­ë,ýÊ&?©ÝýÊ'¶º%²('j["?0ÑÜ¿Ë<0ÑßÿÿN¬Â?¥u·¢?Ë^iÚ¶¬µ©Ýj·]j+2ýÈZ?ð?ØZmjÛayéÝ¡ûazX§{ñh­ìZ??^þÖ¤y§(?Úè?W«Â+a~?«?騯)èuëÿÿò-Â?¥vZ(?X¤zØb³ûa?y(|0ÑÙÖ²³ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿEÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÁ­©Ü?ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿýÓ_ÿÿÿÿÿÿÿÿÿÿÿÿôm·ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÑ_ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿðkjw!ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿýÓ¡é캷¦j×!yÛb?)à~?ð®+^?ëÞ?)àþØb³.?ׯzv©¦\­¢Ø^v'ßz·§¶&¥rZ?ÿÿ!©¢)à?騯/Ý£       ÿr©±Ø«yËeÊ?í?ãÖ«(¦?,yÛh?³ÿâ~ØZ¶f­µêìÿð¨??«yÛhjȦ¦Wj+2r¢?ù²²)®?«b¢{,??-?+-¡·?m§buæ?¢Øÿþ)ÞÉçbjÚ?f«?)ìjwb?Ïéj¶¦z׫¦Z-³ÿÿN¢æåz×??«%zË/z»bq©??âÎ?íjW²zf«?)ÿÿôáyÚ.nWÿµç??Ê!jÆ«zÊ'j{ÿ²ç$¢ëÿ?x§±êí??å¢Ë/z¼???¶?ayÉhrGëz«?Ìÿÿü!z·?²Ø^²Ö§uªÝu¨¬Ë÷!j)â²·¥jدz\??«hºÛhÜaóÿÿκ·!??ޝÚ+µée²ë-?+"²w?uçm¢)©®?Þ¶?ÉçbjÚ?öî´??ûlyèhÂ?ð?/ÿý8b²+?Ê¥¨§¶?èº×ÿý©Ý²?!j÷§¢(v'^jƬ¶?!È?!¢é]v?a?Ïÿb&?Ë"?(?ëa?xÿÿôá¢è!¶Ïÿü ò¢w??Ç¢?Ø^±©?n?­ÿÿÓ?©äÊ?ÿ&?¦k/ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿN?§²æìr¸?yúè?Èÿ?+-þÈÿ?+-þ·ª¹ë-ýúÞzX¬¶Ïè®"¶î?Ë?±Êâmïâ?Ø^JæãyË_?é]¢»hiÙ¢?+-z¼¨º¹??·«²©~º&k?¥¨þ-£øm¶?ÿÿ0ýúÞzX¬¶Ïè®ðyºZïì?ùb²Ñh®¥§û"þX¬·úު笷÷ëyéb²Ûÿ¢¸0?Øÿ?éiþ)í?ä®n7?µø??Òâ²×è®éÿþ+qǬ²&åy«ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿ?ÛiÿÿíyÈÿ?º.¦Ïòj(ýÊ&þèº?ì?ùb²Òâ²Ö«r¯zÆ«zø?Á¦åy«ÿÿÿÿÿÿÿ?ÛiÿÿðÃß­ç¥?Ëlþ?àýªÜ?+Þ³û"þX¬´é]þ?⢻h&éÞëý´Ó_å?ËZ­Èb½ë­ëâ{??æ­þm§ÿÿÃÿªÉÿëÁ¾­¦ïÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿôèº{.nÇ+?·?®?¬?ùb²ßì?ùb²ßëz«?²ßß­ç¥?Ëlþ?àÂ+aþéì¹»®&Þþ)íä®n7?µø??Ú+¶??)â²×«Ê?«?é?z»!??ë¢f°yºZïà¢Úÿ?ÛiÿÿðÃß­ç¥?Ëlþ?àÿ?¥¨þÈÿ?+-?ázZÿ²/å?Ëÿ­ê®zËÿ~·??+-³ú+?­?ø^??â?Ø^JæãyË_?é].+-~?î?ÿⱧzË"nW?·ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿøm¶?ÿþ×??ø+¢êlÿ&¡¢Ü¢oà®?©þÈÿ?+-.+-j·!?÷¬j·¯?ìnW?·ÿÿÿÿÿÿøm¶?ÿÿ0ýúÞzX¬¶Ïè®Ú­Èb½ë?²/å?ËN?ßé®*+¶?nîÿÛM5þX¬µªÜ?+Þ±ªÞ¾'°i¹^jßá¶Úÿÿü0Ãú¬?ùÞ·üêÚn
Answered bybowen.liu 6 years 10 months 21 days
Joseph,It depends on whether you are designing a system with SDP (single die package) or DDP (dual die package) DRAM devices.  If it is SDP, it doesn't matter which topology you use, both daisy-chain and double-T topologies should work fine for you, but if you are using DDP device, then double-T topology works better than daisy-chain in term of giving better system margin.  Even though daisy-chain topology (common for DDR3) can distribute load effect to improve margin, but it normally can cause some reflections among loads, and it is worse for DDP case.  I believe that's why DDR3/L RC-D (daisy-chain with DDP device) was only supported up to 1066MTs.  Like other people suggested, you can always run some simulation to verify which topology works better for you when you have doubts like this.Thanks,Bowen-----
Answered bybrian.p.moran 6 years 10 months 21 days
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Answered bybrian.p.moran 6 years 10 months 21 days
Joseph,I have seen the Tee-Tee or the hybrid Tee-Daisy topology used in some instances.  You are correct that theTee-Tee is a pain to route and usually requires a type 4 MB.  We do employ it in some LPDDR3 memory downconfigurations.  In either case, it does require some impedance compensation between the main trunk andthe tee branches in order to optimize.  This is different than the tree topology used in DDR2, in that the lengthto all loads is matched.  Where we found the Tee-Tee particularly interesting is when using multi-die pkgs.  Thedaisy chain topology does not work well with high capacitance loads, such as you can have with LPDDR3 DDPand QDP devices.  You can get excessive ledging and ringback in the first few nodes in the daisy chain. This isthe reason the Tee-Tee topology was developed.  However, if you are supporting only SDPdevices then the daisy chain is the most straightforward. Brian MoranMemory Interface TechnologyClient PlatformsIntel Corporation-----
Answered bymgreim001 6 years 10 months 21 days
Love to know who this vendor is.....;-)going from DDR2 to DDR3 folks went fly by for a reason.  I recommend makingthem prove why ITHO a tree structure offers more margin than the fly by.Micron has some great papers on point to point design on chip downimplementations.   See if that offers any clarity.Otherwise, I would recommend running sims both ways and showing why nondouble T is the way to go.  Trust but always verify.Just my 0.02.   Rambus way back when said I could do short or long channeldesign and nothing else.  They were wrong too, but then again I can be a SIrebel at times.....;-)-Michael.We will either find a way or make one   - HannibalIn the middle of every difficulty lies opportunity   - Al EinsteinIf you think you can do something or you thinkyou can't, in both cases you are probably right   - H FordAnd if I claim to be a wise man it surely means I'm paid too much......;-)On Mon, Jan 13, 2014 at 8:06 PM, Joseph Aday  wrote:> Hi Everyone,>> Has>  anyone tried using a double-tee topology with their> address/command/control signals in DDR3L/LPDDR3?  This would be instead of> the standard daisy-chain,> with an Rtt at the end of the line.>> For example, take a controller with four memory nodes.  It would look like> this (think of DDR2 days):>>                                           - RX>                          - Branch -|>                         |                  - RX> TX ----------------- Rtt>                         |                 - RX>                          - Branch-|>                                           - RX>> To ensure matched timing for write leveling, this would even apply to the> differential clock.  I am doing memory-down (chips directly on the> PWB as opposed to DIMMs.. if that matters?)>> Compared>  to a simple daisy chain, my simulations show this to be a bad idea both>  in eye diagram margins and in s-parameter plots.  The double tee has> less vertical / horizontal eye margin.  The double-tee also has a> resonant "suck out" in insertion loss very close to the clock frequency,>  whereas the standard daisy-chain is relatively flat out to 3GHz.>> Our>  chip vendor tells us this is needed to improve the eye diagram, but I> can't see how or why.  This is also a pain to route.. and so I have no> good ideas as to why I should do this :)>> Am I missing something?  Thoughts?  Anyone else in the same boat? :)>> Thank you,> Joseph Aday> 
Answered byprashant.jaiswar 6 years 10 months 21 days
fly by topology is helpful in DIMM routing.As Moran has mentioned it would be difficult to route double tee. Thiswould eat up your timing margins, you would need a careful simulationdone. Write leveling is a feature suggest to be used in DIMM type DDR3memory configurations.Sent from my Windows PhoneFrom: Surjendra GoswamiSent: 14-01-2014 23:24To: brian.p.moran@xxxxxxxxxCc: josephaday@xxxxxxxxx; si-list@xxxxxxxxxxxxxSubject: [SI-LIST] Re: DDR3-1600 Double-Tee TopologyJoseph,DDR3 supports write leveling  and hence the fly-by topology is the mostprolific an DDR3 designs.The double tee topology was used for DDR2 and had some downside in theimpedance discontinuities due to branching along the routes causing obviousmargin losses.RegardsSurjendraOn Tue, Jan 14, 2014 at 10:25 PM, Moran, Brian P wrote:> Joseph,>> I have seen the Tee-Tee or the hybrid Tee-Daisy topology used in some> instances.  You are correct that the> Tee-Tee is a pain to route and usually requires a type 4 MB.  We do employ> it in some LPDDR3 memory down> configurations.  In either case, it does require some impedance> compensation between the main trunk and> the tee branches in order to optimize.  This is different than the tree> topology used in DDR2, in that the length> to all loads is matched.  Where we found the Tee-Tee particularly> interesting is when using multi-die pkgs.  The> daisy chain topology does not work well with high capacitance loads, such> as you can have with LPDDR3 DDP> and QDP devices.  You can get excessive ledging and ringback in the first> few nodes in the daisy chain. This is> the reason the Tee-Tee topology was developed.  However, if you are> supporting only SDP> devices then the daisy chain is the most straightforward.>> Brian Moran> Memory Interface Technology> Client Platforms> Intel Corporation>> -----