Measurement point for DDR3

Hi experts,I am validating pre-silicon an embedded DDR3 interface with simulation. The system is an ASIC connected to a DIMM with an 8 device DIMM.Where is the appropiate place to probe the simulation for timing and voltage measurements to check against the JEDEC specifications during a write operation?I can probe either at the ball of the memory device or, since it is a simulation, inside the memory package at the pad. The signalling at the pad looks cleaner and gives more margin than if I measure at the ball of the device.Cheers,Ted
ted.clark 7 years 3 months 10 days

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Answered byHermann.Ruckerbauer 7 years 2 months 9 days
Hello,just some short comments on die vs. pin on DDR2/3 DRAMs:- The spec clearly states, that the test point is at the Pin. So theDRAM vendors needs to make sure that the device can handle setup/holdtimes that are supplied at the pin ==> The package effects need to beconsidered from the DRAM vendor!- nevertheless, as already stated: The really interesting signal is theone that is suplied ot the pad (or even better to the input of anyreceiver in the DRAM).==>  so I often take a look to both, the pin and the pad and if I seebig differences I need to use some engineering judgement how to dealwith it.But this brings one important point that is often not considered:looking to the waveform on the die and using the spec values for tSHthat are defined at the pin now does include the package twice. We havesome doublecounting of the package effects as they are in the Spec aswell as in the simulation (when looking to the waveform at the die). SoI often did an estimation on package effects and removed them whencalculating the timing budget. Problem here is, that the normal RLCpackage model that is delivered with IBIS is getting very close to theborders of usability for DDR3 speeds vs. package size.So when really trying to take a look to package vs. die waveforms oneshould:- use better package models than just lumped RLC models- Clearly define and adjust how the Timing budget is calculated (basedon pin or die waveform).- take double counting of package effecs into account when comparingSpec vs. Simulated margins- Check both signals (pin and die) and use engineering judgement how tojudge the differences.Regarding TX out measurements at the DRAM:I think the comment was not on basic signal integrity, but to verifythat over/undershoots are in the device limits.When remembering correct the over/undershoot spec was defined in theinput section, where I see it most critical.I have seen fails that have been caused by overshoots that injectedelectrons into sensitive circuits on the DRAM die. If this happensduring transmit operations from the DRAMs (aka Reads) I can imagin asimilar issue that will then disturb the following writes. Neverthelessso far check over/undershoot only as input measurement.This might only apply to non terminated systems as with termination onDQ bus ususally there is anyhow now over/undershoot and CA bus is notdriven by the DRAM.All other TX out parameters (e. g. Output slew rate) are only definedinto a termination and it does not make sense to do this measurements ina real system.Best regardsHermannEKH - EyeKnowHowHermann Ruckerbauerwww.EyeKnowHow.deHermann.Ruckerbauer@xxxxxxxxxxxxxItzlinger Strasse 21a94469 DeggendorfTel.:   +49 (0)991 / 29 69 29 05Mobile: +49 (0)176  / 787 787 77Fax:    +49 (0)3212 / 121 9008schrieb Siddharth Rajagopalan:> hi mustafa,> Is probing at the TX pin really representative of the output of the> transmitter when connected to the channel?? i suppose it'll be the sum of> TX output plus the reflections from the line.> Regards,> Siddharth Rajagopalan> Signal integrity engineer,> Cisco systems> Mobile: +91 725 9277122> direct: +91 8044266229> official email: sidrajag@xxxxxxxxx>>>>> On Thu, Sep 26, 2013 at 11:14 AM, Feng Wu  wrote:>>> Hi Suhua>> the signal at die pad is the one seen by receiver finally.>> But the spec could be for the signal at the pin, such as DDR3.>> -->> B.R.>> Feng Wu (后�)>>>> ------------->> Signal Integrity Engineer>> Cisco Shanghai>> ------------->> 2013/9/26 wangsuhua >>>>> so my understand is we should probe at die when simulation, because die>> is>>> last receive, a real signal. is it right>>>>>>> Date: Mon, 2 Sep 2013 10:22:44 +0800>>>> Subject: [SI-LIST] Re: Measurement point for DDR3>>>> From: wufengthu@xxxxxxxxx>>>> To: yousufs432@xxxxxxxxx>>>> CC: ted.clark@xxxxxxx; si-list@xxxxxxxxxxxxx>>>>>>>> Hi Yousuf>>>> I agree that usually the waveform at pin is worse than the waveform at>>> die,>>>> especially for Point to Point topology.>>>> However I ever saw the exception in other topology, such as DDR3>> address>>>> bus. Due to the multiple reflection, the waveform at pin is better than>>>> waveform at die.>>>> The waveform at die show stronger ringback than the one at pin.>> sometimes>>>> it will go cross the Vin(DC) at die while perfect good at pin.>>>> This is terrible, because you can't find this problem in the>> measurement.>>>> The only way to find it is the simulation.>>>> Thanks>>>> Feng>>>> -->>>> B.R.>>>> Feng Wu (�â·ã)>>>>>>>> ------------->>>> Signal Integrity Engineer>>>> Cisco Shanghai>>>> ------------->>>>>>>> 2013/8/29 Mustafa Yousuf >>>>>>>>> Hi Ted,>>>>>>>>>> In simulation you can probe at both the pin (ball) or pad of the>> memory>>>>> device. The signal would be cleaner at the pad since it is closest to>>>>> termination but at the ball there some reflection involved and that>>> makes>>>>> the signal more noisy.>>>>> You can also probe at the sending device (Tx) pin to make sure the>>> signal,>>>>> the overshoot, undershoot, etc at the Tx are appropriate and within>> the>>>>> device tolerance and so on.>>>>>>>>>> In lab measurements though, you want to probe at the closest point>> you>>> can>>>>> to pin or pad since pin or pad may not be reachable.>>>>>>>>>>>>>>> Regards,>>>>>>>>>> Mustafa>>>>>>>>>>>>>>>>>>>> -----
Answered bymaxsidhu 7 years 2 months 9 days
hi mustafa,Is probing at the TX pin really representative of the output of thetransmitter when connected to the channel?? i suppose it'll be the sum ofTX output plus the reflections from the line.Regards,Siddharth RajagopalanSignal integrity engineer,Cisco systemsMobile: +91 725 9277122direct: +91 8044266229official email: sidrajag@xxxxxxxxxOn Thu, Sep 26, 2013 at 11:14 AM, Feng Wu  wrote:> Hi Suhua> the signal at die pad is the one seen by receiver finally.> But the spec could be for the signal at the pin, such as DDR3.> --> B.R.> Feng Wu (吴�)>> -------------> Signal Integrity Engineer> Cisco Shanghai> -------------> 2013/9/26 wangsuhua >> > so my understand is we should probe at die when simulation, because die> is> > last receive, a real signal. is it right> >> > > Date: Mon, 2 Sep 2013 10:22:44 +0800> > > Subject: [SI-LIST] Re: Measurement point for DDR3> > > From: wufengthu@xxxxxxxxx> > > To: yousufs432@xxxxxxxxx> > > CC: ted.clark@xxxxxxx; si-list@xxxxxxxxxxxxx> > >> > > Hi Yousuf> > > I agree that usually the waveform at pin is worse than the waveform at> > die,> > > especially for Point to Point topology.> > > However I ever saw the exception in other topology, such as DDR3> address> > > bus. Due to the multiple reflection, the waveform at pin is better than> > > waveform at die.> > > The waveform at die show stronger ringback than the one at pin.> sometimes> > > it will go cross the Vin(DC) at die while perfect good at pin.> > > This is terrible, because you can't find this problem in the> measurement.> > > The only way to find it is the simulation.> > > Thanks> > > Feng> > > --> > > B.R.> > > Feng Wu (�â·ã)> > >> > > -------------> > > Signal Integrity Engineer> > > Cisco Shanghai> > > -------------> > >> > > 2013/8/29 Mustafa Yousuf > > >> > > > Hi Ted,> > > >> > > > In simulation you can probe at both the pin (ball) or pad of the> memory> > > > device. The signal would be cleaner at the pad since it is closest to> > > > termination but at the ball there some reflection involved and that> > makes> > > > the signal more noisy.> > > > You can also probe at the sending device (Tx) pin to make sure the> > signal,> > > > the overshoot, undershoot, etc at the Tx are appropriate and within> the> > > > device tolerance and so on.> > > >> > > > In lab measurements though, you want to probe at the closest point> you> > can> > > > to pin or pad since pin or pad may not be reachable.> > > >> > > >> > > > Regards,> > > >> > > > Mustafa> > > >> > > >> > > >> > > > -----
Answered bywufengthu 7 years 2 months 11 days
Hi Suhuathe signal at die pad is the one seen by receiver finally.But the spec could be for the signal at the pin, such as DDR3.-- B.R.Feng Wu (吴�)-------------Signal Integrity EngineerCisco Shanghai-------------2013/9/26 wangsuhua > so my understand is we should probe at die when simulation, because die is> last receive, a real signal. is it right>> > Date: Mon, 2 Sep 2013 10:22:44 +0800> > Subject: [SI-LIST] Re: Measurement point for DDR3> > From: wufengthu@xxxxxxxxx> > To: yousufs432@xxxxxxxxx> > CC: ted.clark@xxxxxxx; si-list@xxxxxxxxxxxxx> >> > Hi Yousuf> > I agree that usually the waveform at pin is worse than the waveform at> die,> > especially for Point to Point topology.> > However I ever saw the exception in other topology, such as DDR3 address> > bus. Due to the multiple reflection, the waveform at pin is better than> > waveform at die.> > The waveform at die show stronger ringback than the one at pin. sometimes> > it will go cross the Vin(DC) at die while perfect good at pin.> > This is terrible, because you can't find this problem in the measurement.> > The only way to find it is the simulation.> > Thanks> > Feng> > --> > B.R.> > Feng Wu (�â·ã)> >> > -------------> > Signal Integrity Engineer> > Cisco Shanghai> > -------------> >> > 2013/8/29 Mustafa Yousuf > >> > > Hi Ted,> > >> > > In simulation you can probe at both the pin (ball) or pad of the memory> > > device. The signal would be cleaner at the pad since it is closest to> > > termination but at the ball there some reflection involved and that> makes> > > the signal more noisy.> > > You can also probe at the sending device (Tx) pin to make sure the> signal,> > > the overshoot, undershoot, etc at the Tx are appropriate and within the> > > device tolerance and so on.> > >> > > In lab measurements though, you want to probe at the closest point you> can> > > to pin or pad since pin or pad may not be reachable.> > >> > >> > > Regards,> > >> > > Mustafa> > >> > >> > >> > > -----
Answered bystar_wang1 7 years 2 months 11 days
so my understand is we should probe at die when simulation, because die is last receive, a real signal. is it right> Date: Mon, 2 Sep 2013 10:22:44 +0800> Subject: [SI-LIST] Re: Measurement point for DDR3> From: wufengthu@xxxxxxxxx> To: yousufs432@xxxxxxxxx> CC: ted.clark@xxxxxxx; si-list@xxxxxxxxxxxxx> > Hi Yousuf> I agree that usually the waveform at pin is worse than the waveform at die,> especially for Point to Point topology.> However I ever saw the exception in other topology, such as DDR3 address> bus. Due to the multiple reflection, the waveform at pin is better than> waveform at die.> The waveform at die show stronger ringback than the one at pin. sometimes> it will go cross the Vin(DC) at die while perfect good at pin.> This is terrible, because you can't find this problem in the measurement.> The only way to find it is the simulation.> Thanks> Feng> -- > B.R.> Feng Wu (Îâ·ã)> > -------------> Signal Integrity Engineer> Cisco Shanghai> -------------> > 2013/8/29 Mustafa Yousuf > > > Hi Ted,> >> > In simulation you can probe at both the pin (ball) or pad of the memory> > device. The signal would be cleaner at the pad since it is closest to> > termination but at the ball there some reflection involved and that makes> > the signal more noisy.> > You can also probe at the sending device (Tx) pin to make sure the signal,> > the overshoot, undershoot, etc at the Tx are appropriate and within the> > device tolerance and so on.> >> > In lab measurements though, you want to probe at the closest point you can> > to pin or pad since pin or pad may not be reachable.> >> >> > Regards,> >> > Mustafa> >> >> >> > -----
Answered bywufengthu 7 years 3 months 5 days
Hi YousufI agree that usually the waveform at pin is worse than the waveform at die,especially for Point to Point topology.However I ever saw the exception in other topology, such as DDR3 addressbus. Due to the multiple reflection, the waveform at pin is better thanwaveform at die.The waveform at die show stronger ringback than the one at pin. sometimesit will go cross the Vin(DC) at die while perfect good at pin.This is terrible, because you can't find this problem in the measurement.The only way to find it is the simulation.ThanksFeng-- B.R.Feng Wu (Îâ·ã)-------------Signal Integrity EngineerCisco Shanghai-------------2013/8/29 Mustafa Yousuf > Hi Ted,>> In simulation you can probe at both the pin (ball) or pad of the memory> device. The signal would be cleaner at the pad since it is closest to> termination but at the ball there some reflection involved and that makes> the signal more noisy.> You can also probe at the sending device (Tx) pin to make sure the signal,> the overshoot, undershoot, etc at the Tx are appropriate and within the> device tolerance and so on.>> In lab measurements though, you want to probe at the closest point you can> to pin or pad since pin or pad may not be reachable.>>> Regards,>> Mustafa>>>> -----
Answered bywufengthu 7 years 3 months 5 days
Hi TedI ever asked the same question to Micron's AE.The JEDEC spec is specified at memory package pin. however you can also useit as the die pad for Micron devices.Unlike Serdes, the spec are the same for both package pin and die pad.In my previous projects, I use the waveform quality and timing at die pinto sign off my design (I would like to keep some margin for SSN in case ofSI simulatn only).And I use the waveform at fanout via to correlate my simulation andmeasurement.If you stll have concern,just send the waveform at both pin and pad toMicron.ThanksFeng-- B.R.Feng Wu (Îâ·ã)-------------Signal Integrity EngineerCisco Shanghai-------------2013/8/28 Ted Clark > Hi experts,> I am validating pre-silicon an embedded DDR3 interface with simulation.> The system is an ASIC connected to a DIMM with an 8 device DIMM.>> Where is the appropiate place to probe the simulation for timing and> voltage measurements to check against the JEDEC specifications during a> write operation?>> I can probe either at the ball of the memory device or, since it is a> simulation, inside the memory package at the pad. The signalling at the pad> looks cleaner and gives more margin than if I measure at the ball of the> device.>> Cheers,> Ted>>> 
Answered bywufengthu 7 years 3 months 5 days
-- B.R.Feng Wu (Îâ·ã)-------------Signal Integrity EngineerCisco Shanghai-------------2013/8/28 Ted Clark > Hi experts,> I am validating pre-silicon an embedded DDR3 interface with simulation.> The system is an ASIC connected to a DIMM with an 8 device DIMM.>> Where is the appropiate place to probe the simulation for timing and> voltage measurements to check against the JEDEC specifications during a> write operation?>> I can probe either at the ball of the memory device or, since it is a> simulation, inside the memory package at the pad. The signalling at the pad> looks cleaner and gives more margin than if I measure at the ball of the> device.>> Cheers,> Ted>>> 
Answered byamiagra2 7 years 3 months 10 days
Sent from my iPhoneOn Aug 28, 2013, at 8:38 AM, "Scott McMorrow"  wrote:> Ted> DDR3 timing is specified at the pins of the memory device.  (I know,> stupid, but true.)  At this ASIC it is wherever you'd like it to be.> > regards,> > Scott> > > On Wed, Aug 28, 2013 at 11:28 AM, Ted Clark  wrote:> >> Hi experts,>> I am validating pre-silicon an embedded DDR3 interface with simulation.>> The system is an ASIC connected to a DIMM with an 8 device DIMM.>> >> Where is the appropiate place to probe the simulation for timing and>> voltage measurements to check against the JEDEC specifications during a>> write operation?>> >> I can probe either at the ball of the memory device or, since it is a>> simulation, inside the memory package at the pad. The signalling at the pad>> looks cleaner and gives more margin than if I measure at the ball of the>> device.>> >> Cheers,>> Ted>> >> >> 
Answered byscott 7 years 3 months 10 days
TedDDR3 timing is specified at the pins of the memory device.  (I know,stupid, but true.)  At this ASIC it is wherever you'd like it to be.regards,ScottOn Wed, Aug 28, 2013 at 11:28 AM, Ted Clark  wrote:> Hi experts,> I am validating pre-silicon an embedded DDR3 interface with simulation.> The system is an ASIC connected to a DIMM with an 8 device DIMM.>> Where is the appropiate place to probe the simulation for timing and> voltage measurements to check against the JEDEC specifications during a> write operation?>> I can probe either at the ball of the memory device or, since it is a> simulation, inside the memory package at the pad. The signalling at the pad> looks cleaner and gives more margin than if I measure at the ball of the> device.>> Cheers,> Ted>>> 
Answered byyousufs432 7 years 3 months 10 days
Hi Ted,In simulation you can probe at both the pin (ball) or pad of the memorydevice. The signal would be cleaner at the pad since it is closest totermination but at the ball there some reflection involved and that makesthe signal more noisy.You can also probe at the sending device (Tx) pin to make sure the signal,the overshoot, undershoot, etc at the Tx are appropriate and within thedevice tolerance and so on.In lab measurements though, you want to probe at the closest point you canto pin or pad since pin or pad may not be reachable.Regards,Mustafa -----