DDR2 spacing rule

Hi All,Why data lines of same byte in ddr2 routed together?As we know all the datalines in a DDR2 running at same frequency and if we route byte0 and byte1at same length,why do we need to maintain different trace-trace spacing forsame byte and different byte?-- bala
balaseven 7 years 4 months 11 days

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Answered bybrian.p.moran 7 years 4 months 10 days
Bala,One reason for the larger spacing between byte lanes is that byte lanes can be routed at different lengths andthere can be significant phase offset between byte lanes.  Not so much in DDR2, but certainly in DDR3.  Out of phasextalk is more problematic that xtalk within a byte lane.  Since there are only 7 boundaries between byte lanes itscommon to allocate more spacing to these boundaries in order to avoid or reduce out of phase xtalk.  Brian MoranMemory Interface TechnologyClient PlatformsIntel Corporation-----
Answered bybalaseven 7 years 4 months 10 days
Hi Prashant,How it helps to meet timing budget..some slight timing pull-in/out might bethere due to crosstalk..how this crosstalk varies w.r.t byte to bye..We areallowed to have 2X spacing for same data byte but 3X needed for differentbyte...Though DQS is different,data is running at same frequency anddelay.How/Why there is a difference in xtalk amplitude?Thanks for your time.RegardsbalaOn Sun, Jul 28, 2013 at 10:06 PM, Prashant Jaiswar  wrote:> DQS is defiend per byte lane and the data is sampled with respect to DQS> of each byte lane during read/write operations.> This helps meet the timing budget/relationship from DRAM controller/memory> chip per se.>> On Sun, Jul 28, 2013 at 2:55 PM, bala  wrote:>>> Hi All,>> Why data lines of same byte in ddr2 routed together?As we know all the>> data>> lines in a DDR2 running at same frequency and if we route byte0 and byte1>> at same length,why do we need to maintain different trace-trace spacing>> for>> same byte and different byte?>>>> -->> bala>>>>>> 
Answered byprashant.jaiswar 7 years 4 months 11 days
DQS is defiend per byte lane and the data is sampled with respect to DQS ofeach byte lane during read/write operations.This helps meet the timing budget/relationship from DRAM controller/memorychip per se.On Sun, Jul 28, 2013 at 2:55 PM, bala  wrote:> Hi All,> Why data lines of same byte in ddr2 routed together?As we know all the data> lines in a DDR2 running at same frequency and if we route byte0 and byte1> at same length,why do we need to maintain different trace-trace spacing for> same byte and different byte?>> --> bala>>> 
Answered byyousufs432 7 years 4 months 11 days
Hi Bala,Not trying to repeat what was said but to perhaps put more clearly.Each byte is associated with its own DQS and must be length matchedaccordingly within the byte.DQS's need not to be length matched tightly together but they need to remainlength matched to CLK within 1/4 CLK cycle.Each bye with its DQS could be toggling differently from other bytes andcould be routed in different location or even different layer from otherbytes. This means exposure of each byte to different crosstalk (XTalk)environment although XTalk should be minimized for each byte. Hence byte tobyte spacing should be as large as possible and larger than trace to tracespacing within the byte. This is to minimize XTalk between bytes which helpsmaintain timing control for the entire bus.I hope this helps.Regards,Mustafa -----
Answered byweirsi 7 years 4 months 11 days
DQS is per byte.SteveOn 7/28/2013 2:25 AM, bala wrote:> Hi All,> Why data lines of same byte in ddr2 routed together?As we know all the data> lines in a DDR2 running at same frequency and if we route byte0 and byte1> at same length,why do we need to maintain different trace-trace spacing for> same byte and different byte?>-- Steve WeirIPBLOX, LLC1580 Grand Point WayMS 34689Reno, NV  89523-9998www.ipblox.com(775) 299-4236 Business(866) 675-4630 Toll-free(707) 780-1951 FaxAll contents Copyright (c)2013 IPBLOX, LLC.  All Rights Reserved.This e-mail may contain confidential material.If you are not the intended recipient, please destroy all recordsand notify the sender.