DDR3 routing Topology selection

HiWe are designing a custom board where 2 DDR3 chips (533MHz) are interfacedwith processor. There are two routing toplogies which we are consideringfor our layout.1. T topology2. Fly-By topologyWe have done pre-layout SI simulation using hyperlynx. As we know  for DDR3flyby topology is recommended by JEDEC but according to our simulationresults  T topology is looking better.In T topology overshoot is coming 1.6V and undershoot is -0.1V and inFly-By topology overshoot is coming at 1.225V and undershoot at 240mV. I amattaching snapshots here. Please confirm what topology flyby or T topologywe should prefer for our board.RegardsSonu Goyal
sonu.goyal 7 years 7 months 12 days

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Answered byrameshnatesh 7 years 7 months 6 days
The length matching requirement depends on the DDR PHY's (on the processor)ability to level the lane delay skews. The delay lines in the PHY have amax. limit and the lane-to-lane skew requirement is borne out of this limit.To answer your question:a) It is NOT important to length match CK with DQ/DQS. Write levelingcompensates for the skews (again, within the max. limit)b) As I mentioned above, you need to conform to the length matchingrequirements laid out by processor.-regards,RameshOn Tue, Jun 25, 2013 at 12:14 PM, Vinod Kumar wrote:> One more question>> Whether we are using T or Fly by, how important it is to length match> data/strobe signals with clock signal?> General layout guidelines for all processors mention some length matching> requirements, but is it really required?>> Regards,> Vinod>> -----
Answered byvinod.kumar 7 years 7 months 6 days
One more questionWhether we are using T or Fly by, how important it is to length matchdata/strobe signals with clock signal?General layout guidelines for all processors mention some length matchingrequirements, but is it really required?Regards,Vinod-----
Answered bysen.velmurugan 7 years 7 months 11 days
Vinod,You need to check the setup n hold time margin for the choice of topology before finalizing.ThanksSenMsg: #12 in digestFrom: "Vinod Kumar"Subject: [SI-LIST] Re: DDR3 routing Topology selectionDate: Wed, 19 Jun 2013 17:09:45 +0530Hi Hermann,Thank you very much for your inputs.And extra time for calibration is not an issue. My main concern is thesupport for DDR3 calibration with the BSP that I got from vendor.In the reference board, there are four DDR3 chips and T-topology is used andthere are no terminations. So I am not sure if write leveling is supportedin the reference code. I was actually thinking about those additionalefforts if there is no code support. BTW, I am inclined more towards fly bytopology.Regards,Vinod
Answered bydoltbird1972 7 years 7 months 12 days
Whether you need to calibrate the write leveling depends how much the timingdelay mismatch among your Address signals.1. If the timing mismatch is within your controller's specification, thenjust forget it;2. if it is out of the specification, you may choose a) do write leveling b)compensate the delay by tuning the timing delay in Data signals(tricky). Regards!ShaoPengIEEE Member, Senior SI Consultant and PCB Engineer-----
Answered bydoltbird1972 7 years 7 months 12 days
Sonu,As for 2 DDR3 chips on your board, it does not matter what kind of topologyyou are using. Just thinking about convenience for your layout.( The thing will be totally different when more than 4 chips. )Regards!ShaoPengIEEE Member, Senior SI Consultant and PCB Engineer-----
Answered byvinod.kumar 7 years 7 months 12 days
Hi Hermann, Thank you very much for your inputs.And extra time for calibration is not an issue. My main concern is thesupport for DDR3 calibration with the BSP that I got from vendor. In the reference board, there are four DDR3 chips and T-topology is used andthere are no terminations. So I am not sure if write leveling is supportedin the reference code. I was actually thinking about those additionalefforts if there is no code support. BTW, I am inclined more towards fly bytopology.Regards,Vinod-----
Answered byvinod.kumar 7 years 7 months 12 days
Hi Hermann,The overshoot/undershoot problem for T-routing is solved by changing thedrive impedance on controller side.I am working along with Sonu on this and the data given by Sonu was for 34Ohm driving impedance. For 40Ohm driving impedance, the voltage swing iswell within 0V to 1.5V.Now question is whether the efforts required for DDR3 calibration/writeleveling for Fly By topology are worth its SI value for a two chip DDR3solution. We are still pondering on it.Regards,Vinod-----
Answered byHermann.Ruckerbauer 7 years 7 months 12 days
Hello Vinod,my comment was not that I would be concerned regarding this overshoots,it was just that it looks different than what was mentioned in the text.Solving this via Drive strength setting is the right way to do.Regarding the Write leveling:Does it hurt you when the calibration are executed? it might take someshort time at powerup, but if you are not critical on this one I wouldleave it in.Otherwise you have to do quite some measurements to figure out the bestsettings e. g. for PVT variations (not really T, and maybe not V, butProcess is considered by the calibration routines).I had concerns in the beginning when these routines have beenintroduced, but in the meantime they are really robust.So if there is nor specific reason (like Power up time) I would utilizethis feature in any hardware ..HermannAm 19.06.2013 12:03, schrieb Vinod Kumar:> Hi Hermann,>> The overshoot/undershoot problem for T-routing is solved by changing the> drive impedance on controller side.> I am working along with Sonu on this and the data given by Sonu was for 34> Ohm driving impedance. For 40Ohm driving impedance, the voltage swing is> well within 0V to 1.5V.>> Now question is whether the efforts required for DDR3 calibration/write> leveling for Fly By topology are worth its SI value for a two chip DDR3> solution. We are still pondering on it.>> Regards,> Vinod>> -----
Answered byHermann.Ruckerbauer 7 years 7 months 12 days
Hello,for two devices at 533 you might have a chance to work without CATermination for the T-Branch.For Flyby this might not be possible.Regarding your comments it looks T is having higher overshoots andtherefore I would excpect FlyBy to show better SI (what is differentthan what you write).T seems to have overshoots, while the levels for FlyBy seems niclyterminated and therefore not even reaching the full swing voltage rails ..Best regardsHermannEKH - EyeKnowHowHermann Ruckerbauerwww.EyeKnowHow.deHermann.Ruckerbauer@xxxxxxxxxxxxxItzlinger Strasse 21a94469 DeggendorfTel.:   +49 (0)991 / 29 69 29 05Mobile: +49 (0)176  / 787 787 77Fax:    +49 (0)3212 / 121 9008schrieb Doltbird1972:> Sonu,> As for 2 DDR3 chips on your board, it does not matter what kind of topology> you are using. Just thinking about convenience for your layout.> ( The thing will be totally different when more than 4 chips. )>> Regards!>> ShaoPeng> IEEE Member, Senior SI Consultant and PCB Engineer>> -----
Answered byhanymhfahmy 7 years 7 months 12 days
Hi Sonu. Flyby was developed by JEDEC for clock, address/command andcontrol signals. We find that T-topo is better for data bus. Check all DIMMrouting that data bus is T-topology. Pls pay attention to short stubs ofthe Sdram connection.  Hope this helps.On Jun 19, 2013 10:35 AM, "Sonu Goyal"  wrote:> Hi> We are designing a custom board where 2 DDR3 chips (533MHz) are interfaced> with processor. There are two routing toplogies which we are considering> for our layout.> 1. T topology> 2. Fly-By topology>> We have done pre-layout SI simulation using hyperlynx. As we know  for DDR3> flyby topology is recommended by JEDEC but according to our simulation> results  T topology is looking better.>> In T topology overshoot is coming 1.6V and undershoot is -0.1V and in> Fly-By topology overshoot is coming at 1.225V and undershoot at 240mV. I am> attaching snapshots here. Please confirm what topology flyby or T topology> we should prefer for our board.>> Regards> Sonu Goyal>>>>