ddr2-ringing and non monotonous conditions

Hi,*In DDr2 simulations, How to reduce ringing and non monotonous conditionswhen we have a point to multipoint topology and unequal loads?** **Please suggest me some good ideas to overcome.*-- Best Regards,Balamanikandan.K
kbmanick 7 years 5 months 21 days

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Answered bykimswitch 7 years 5 months 21 days
How about read "DDR2 UDIMM Design Specification" posted by JEDEC.you can find it at www.jedec.org--- In si-list@xxxxxxxxxxxxxxx, Balamanikandan K  wrote:>> Hi,> *In DDr2 simulations, How to reduce ringing and non monotonous conditions> when we have a point to multipoint topology and unequal loads?*> > * *> > *Please suggest me some good ideas to overcome.*> > -- > Best Regards,> Balamanikandan.K> > > 
Answered byHermann.Ruckerbauer 7 years 5 months 21 days
Hello Balamanikandan,Are you talking about DQ or CA bus, solder down or DIMM based ?On both you can try to tweek the length matching to shift any nonmontonics into regions where you don't care.On DQ you can also optimize ODT configuration settings for different Ranks.On CA you can add serial terminations and move you VTT termination toanother place (also on DQ if reall required).for Clock you might have a chance to utlize additional clock drivers onyour controller and implement a different topologyAlso with drive strenght settings you might ave a chance to reduceringings ..These are the usual suspects and with some simulations you should beable to figure out a working configuration ..Best regardsHermannEKH - EyeKnowHowHermann Ruckerbauerwww.EyeKnowHow.deHermann.Ruckerbauer@xxxxxxxxxxxxxItzlinger Strasse 21a94469 DeggendorfTel.:   +49 (0)991 / 29 69 29 05Mobile: +49 (0)176  / 787 787 77Fax:    +49 (0)3212 / 121 9008schrieb Balamanikandan K:> Hi,> *In DDr2 simulations, How to reduce ringing and non monotonous conditions> when we have a point to multipoint topology and unequal loads?*>> * *>> *Please suggest me some good ideas to overcome.*>