DDR2 length matching address and clock

Dear Experts,This is regarding the trace length matching between DDR2 address and clocksignals.*As per my understanding, **the CLK should be centered within** **addresseye to measure and match the trace length.  i.e. signals should like asshown in figure.****[image: Inline image 1]*****I am using Hyperlynx tool for simulation.Address line is connected from a processor to only one DDR2 DRAM(Not DIMM).I am using a separate PLL clock driver which drives the clock to only oneDRAM.No transmission lines are used (direct connection between driver andmemory). Terminations are provided.*Under direct connections and equal load ( only one DRAM) :***If the length adjustment measurement is to be right, then there should notbe any time difference (skew) between the clock signal and address signalwhen the signal rises at the output of the drivers.We have probed signals at the die as well as the pin of the driver output.But the simulation results show the time difference. Clock signal advancesby 200 ps when compared the address signal.When the skew at the output of the drivers is equal to zero, then only itmakes sense in probing the signals at the receiver and we can adjust andkeep the clock in center of the address eye.Why there is a shift? Is this something related to ibis model? How tocorrect it?*Please clarify the doubts. Please Suggest me good guidelines if theprocedure followed by me is wrong.*-- Best Regards,Balamanikandan.K
kbmanick 7 years 6 months 18 days

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Answered byweirsi 7 years 6 months 18 days
K if you have doubts about your models it is best to talk to the silicon vendor who supplied them.  There are enough reference designs around for DDR2 that you should not have a problem running the model in your environment against a known result.Steve.On 5/21/2013 11:38 PM, Balamanikandan K wrote:> Dear Experts,>> This is regarding the trace length matching between DDR2 address and clock> signals.>> *As per my understanding, **the CLK should be centered within** **address> eye to measure and match the trace length.  i.e. signals should like as> shown in figure.*>>> **> *[image: Inline image 1]*> **>> **>> I am using Hyperlynx tool for simulation.>>> Address line is connected from a processor to only one DDR2 DRAM(Not DIMM).>> I am using a separate PLL clock driver which drives the clock to only one> DRAM.>> No transmission lines are used (direct connection between driver and> memory). Terminations are provided.>> *Under direct connections and equal load ( only one DRAM) :*>> *> *>> If the length adjustment measurement is to be right, then there should not> be any time difference (skew) between the clock signal and address signal> when the signal rises at the output of the drivers.>>> We have probed signals at the die as well as the pin of the driver output.>>> But the simulation results show the time difference. Clock signal advances> by 200 ps when compared the address signal.>>> When the skew at the output of the drivers is equal to zero, then only it> makes sense in probing the signals at the receiver and we can adjust and> keep the clock in center of the address eye.>>> Why there is a shift? Is this something related to ibis model? How to> correct it?>>> *Please clarify the doubts. Please Suggest me good guidelines if the> procedure followed by me is wrong.*>>-- Steve WeirIPBLOX, LLC1580 Grand Point WayMS 34689Reno, NV  89523-9998www.ipblox.com(775) 299-4236 Business(866) 675-4630 Toll-free(707) 780-1951 FaxAll contents Copyright (c)2013 IPBLOX, LLC.  All Rights Reserved.This e-mail may contain confidential material.If you are not the intended recipient, please destroy all recordsand notify the sender.