Power Supply Noise injected Jitter impact on SERDES performance

Hi All,


In my design I have high speed interfaces like DDR4 and PCIe 3.0 interface
operating at their maximum frequency.



I am also dealing with the PDN analysis for core voltage supplies on PCB
for Xilinx ultra-scale FPGA.



I would like to understand how important is it consider board level power
Supply Noise injected from voltage planes and its effects on SERDES
interface like PCIe 3.0 in my simulation.


Could you please let me know how can we model this noise as jitter to
perform channel simulation for eye diagram analysis..?


Thanks in advance..



Regards,

Ramesh Ponnada


rameshp3note 4 years 9 months 2 days

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Answered bycarsona 4 years 9 months 2 days
How are you modelling the on-die and on-package capacitance of the FPGA?
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On 14 January 2016 at 16:57, Ramesh Ponnada wrote:

Hi All,


In my design I have high speed interfaces like DDR4 and PCIe 3.0 interface
operating at their maximum frequency.



I am also dealing with the PDN analysis for core voltage supplies on PCB
for Xilinx ultra-scale FPGA.



I would like to understand how important is it consider board level power
Supply Noise injected from voltage planes and its effects on SERDES
interface like PCIe 3.0 in my simulation.


Could you please let me know how can we model this noise as jitter to
perform channel simulation for eye diagram analysis..?


Thanks in advance..



Regards,

Ramesh Ponnada