ground recessing

Hi experts,
I approach a case about ground recessing. For eight PCIE lanes, the sixteen
AC caps are in parrell to each other. I want to do ground recessing
underneath the caps and therefore the ground recessing becomes a long slot
under sixteen caps.

Although from simulation, the TDR curves are good. However, do you worry
that the signal traces in the eight lanes (especially in the middle) will
not find minimal loop return currents?

Besides TDR, what parameters should I also watch in HFSS for such a case?
crosstalk? EMI parameters?

Regards

--
best wishes,

Jun Zhang


zhangjun5960 4 years 9 months 23 days

16 answers


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Answered byleeritchey 4 years 9 months 22 days
That's good. I'll take one!

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Answered byleeritchey 4 years 9 months 22 days
Beware of unvalidated simulations. They often lead you to incorrect
conclusions.

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Answered byzhangjun5960 4 years 9 months 22 days
Hi Laney,
Happy Christmas!

My AC cap is located on top layer, GND layer 2 has some ground recessing
and the next ground layer is GND layer 4. From my simulation yesterday, I
find that the electric field transform from between the trace and G02 to
between the pad of the cap and G04 suddenly.

I want to know without GND vias to conductor the electric field smoothly,
what bad effects this sudden transform (G02->G04) will happen? Does emi
will become bad? Does crosstalk will become serious?

Anyway I think this sudden transform is bad for return path. But I still
want to know the badness quantitatively.

Hope to your reply

Regards





On Thu, Dec 24, 2015 at 1:40 PM, jun zhang wrote:

Hi Laney,

Thank you very much for your suggestions. Indeed there are large amounts
of return currents in the gnd plane from some text books.

Regards



On Thu, Dec 24, 2015 at 1:31 PM, Orin Laney wrote:

Total return currents in a diff pair sum to zero but they are not
individually zero and still need a local return path. You should use eight
individual slots rather than one big one. The foil straps between slots
let
return currents stay local to the pair.

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Answered bycarson.au 4 years 9 months 22 days
The rise time of some of our signals are ~11ps.
On Fri, Dec 25, 2015 at 11:17 AM, Lee Ritchey
wrote:

All of the traces in the test PCBs were 4.5 mils. Our TDR has a 25 pSec
edge.

I agree that the TDRs in fab shops are not fast and they do not need to be.
Are inferring that I used those TDRs?

Sounds to me like there are a number of people who are trying to make a
rule
true which is not and doing it without proper measurements.

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Answered byscott 4 years 9 months 22 days
Jun
If you are using a 3D full-wave simulator like HFSS, then all will be
revealed. It's just a matter of setting the problem up correctly to
instrument what you want to see. It's also helpful to model the actual
capacitor structure.

Depending on the size of the capacitor, and the placement of the holes, you
can either make the transition better or worse. Detailed modeling and
simulation, or detailed measurement experiments are important in these
cases.

Scott






Scott McMorrow
R&D Consultant
Teraspeed Consulting - A Division of Samtec
16 Stormy Brook Rd
Falmouth, ME 04105
(401) 284-1827 Business
http://www.teraspeed.com

On Thu, Dec 24, 2015 at 11:34 PM, jun zhang wrote:

Hi Laney,
Happy Christmas!

My AC cap is located on top layer, GND layer 2 has some ground recessing
and the next ground layer is GND layer 4. From my simulation yesterday, I
find that the electric field transform from between the trace and G02 to
between the pad of the cap and G04 suddenly.

I want to know without GND vias to conductor the electric field smoothly,
what bad effects this sudden transform (G02->G04) will happen? Does emi
will become bad? Does crosstalk will become serious?

Anyway I think this sudden transform is bad for return path. But I still
want to know the badness quantitatively.

Hope to your reply

Regards





On Thu, Dec 24, 2015 at 1:40 PM, jun zhang wrote:

Hi Laney,

Thank you very much for your suggestions. Indeed there are large amounts
of return currents in the gnd plane from some text books.

Regards



On Thu, Dec 24, 2015 at 1:31 PM, Orin Laney wrote:

Total return currents in a diff pair sum to zero but they are not
individually zero and still need a local return path. You should use
eight
individual slots rather than one big one. The foil straps between slots
let
return currents stay local to the pair.

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Answered byravinder.ajmani 4 years 9 months 22 days
Hi Lee,

Have you used a 4 mil trace feeding an 0402 capacitor. You will see the
impedance dip if proper TDR step is used. The TDR equipment used by most fab
houses is too slow to show the dip.

Regards

Ravinder Ajmani
HGST, a Western Digital company
ravinder.ajmani@xxxxxxxx

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Answered byolaney 4 years 9 months 23 days
I'm designing TDRs fast enough to support your designs.

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Answered byleeritchey 4 years 9 months 23 days
All of the traces in the test PCBs were 4.5 mils. Our TDR has a 25 pSec
edge.

I agree that the TDRs in fab shops are not fast and they do not need to be.
Are inferring that I used those TDRs?

Sounds to me like there are a number of people who are trying to make a rule
true which is not and doing it without proper measurements.

-----
Answered byleeritchey 4 years 9 months 23 days
My logic devices run as fast as 28 Gb/S. what do your run at?

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Answered byolaney 4 years 9 months 23 days
Your logic devices are slower than my logic devices.

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Answered byleeritchey 4 years 9 months 23 days
What impedance dip? You can't even see that. As always, don't do something
like this on speculation.

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Answered byolaney 4 years 9 months 23 days
So true if proper design practices are followed. What happens is the heresy
of, say, using an 0603 capacitor on a .008" trace, and then using the heresy
of compensating for the impedance dip caused by the ~.040 pad width with a
ground cutaway. Better they should use traces and caps of the same or nearly
equal width over a ground plane of proper distance, but in a cram-it-in
world whatya gonna do? So, we smile and keep passing out the SI consulting
business cards...

Orin

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Answered byzhangjun5960 4 years 9 months 23 days
Hi Laney,
Thank you very much for your suggestions. Indeed there are large amounts of
return currents in the gnd plane from some text books.

Regards



On Thu, Dec 24, 2015 at 1:31 PM, Orin Laney wrote:

Total return currents in a diff pair sum to zero but they are not
individually zero and still need a local return path. You should use eight
individual slots rather than one big one. The foil straps between slots let
return currents stay local to the pair.

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Answered bytom 4 years 9 months 23 days
Lee

Is this one of those rules-of-thumb that came about when 1206 or 805
components were used and those pads were large compared to the line widths
employed at the time. Today where 0402 components are used the trade-off
isn't as important? So this practice could be important in some cases and
not in others? And thus an evaluation must be performed to determine if it
is needed in a particular case looking at the characteristics of the whole
channel and not just the section around the caps?

Regards,

Tom Dagostino
971-279-5325
tom@xxxxxxxxxxxxxxxxx

Teraspeed Labs
9999 SW Wilshire Street
Suite 102
Portland, OR 97225


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Answered byleeritchey 4 years 9 months 23 days
Ground recessing is not required, so don't do it. We have built test PCBs
with and without ground recessing and found that there is little change.
What change there is results in more loos at high frequencies when you
remove the ground from under that AC capacitor mounting pads.

I wonder who came up with this rule. Whoever did, did not do any validation
of its worth.

We have entirely too much of this in application notes.

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Answered byolaney 4 years 9 months 23 days
Total return currents in a diff pair sum to zero but they are not
individually zero and still need a local return path. You should use eight
individual slots rather than one big one. The foil straps between slots let
return currents stay local to the pair.

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