Wiring Harnessing SI Question

HI all --

Hoping that list can shed some light on some wire harness related SI
questions at some very, very low speeds.

This list has done a good job teaching me about SI in general, and
especially the concept that while DC (i.e. power delivery) enjoys the
path of least resistance, the same is not true for AC signals (I think
rule of thumb says above 100kHz?).

We have a design where we have a 50-pin connector to our DUT on one
end. This goes to a Y-adapter which turns into 2x 32-pin MIL-STD
circular connectors, then a 6-8ft harness, and then our host / test
equipment box. Earlier this year, we decided to make one cable power,
and one cable data -- logical, right?

Recently though, we've observed severe SI issues when running two data
interfaces simultaneously (1MHz JTAG, and I2C) and this got me
thinking, and re-reading what we designed. Turns out that we were very
thorough in our power and data separation -- there are no grounds in
the data harness at all! This reminded me again of AC return currents
and their wanting to minimize loop area.

Here is my theory / gut feeling -- as the host box clocks out an edge
on lets say TCK, which is driven by a fairly "slow" driver (~15ns rise
time I think), at a frequency of 1MHz, it will leave the driver,
travel on a PCB trace, hop onto the harness, traverse the harness, hop
onto the DUT PCB and into the input device. Not to anthropomorphize
current too much, but at this point having made the long trip to the
DUT, he really wants to get home as fast as possible (and in as small
a loop area as possible). Unfortunately for him, the DC ground return
path is "far" away from the path he arrived on (the two cables kind of
flop around near each other), so he's going to take some path back in
the signal harness -- which could unfortunately be some output driver
that happens to be at '0', or some other data line. This isn't a
ribbon harness, so the conductors just float around in space
constrained only by braid. I think on my scope I can see odd /
increased noise when certain lines are low -- does that low impedance
path to GND encourage return current to flow on that line? If I idle
all I2C traffic, I get no errors on JTAG whatsoever, but when I2C
traffic begins to occur, my JTAG transaction quickly become corrupted.
This is the majority case; I've also observed the inverse behavior
where JTAG squashes I2C.

Am I on the right track here? Or should I be looking more for
reflections / impedance mismatches? This is not a fast interface
overall -- the edge rates aren't ultra-fast and I2C is an open-drain,
slow bus! (I have heard stories of people tuning the VOL strength of
their I2C devices before).

Additionally, I swear I remember reading somewhere an article (or
maybe it was on the list) for a good rule of thumb on how many return
conductors to provide for a given signal harness with n signal
conductors -- does anyone recall this?

Thanks! I'm hoping to work out / test this problem over Thanksgiving
-- it's a frustrating one, but those are also the ones that give you
the best feeling when you defeat them.

KD
movax 4 years 10 months 24 days

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Answered bycorley 4 years 10 months 24 days
In the example you're giving, was that a ribbon cable application? Or
did you actually twist certain cables together to ensure they
presented a known impedance (I assume that would be determined by the
turn ratio).

It was a ribbon cable with adjacent grounds. A twisted pair is similar.
As Lee mentions a shield would also work as a return path. One way or
another your signals need a 'partner' for their dance. ;-) The faster
the edge rate, the more important it becomes.

Chuck



On 2015-11-25 13:24, Krunal Desai wrote:
Thanks for the replies all --

On Wed, Nov 25, 2015 at 12:05 PM, Lee Ritchey
wrote:
Remember that "ground" doesn't have any meaning in the context of
harnesses like this. Transmission lines need partners such as shields
on which their return currents can flow. These shields also prevent
cross talk. Probably what will fix this problem.

This may be a more philosophical question -- do I treat these as
transmission lines despite the relatively 'slow' edge rates / clock
speeds I'm working with? I have no personal objection to this, but my
knowledge-base is such that I have a hard time explaining to people
why I'm treating a bus such as I2C (which is generally an
afterthought) as a transmission line. Certainly on a PCB, I don't
think much about it outside of routing it cleanly / minimizing plane
splits / jumps / etc.

Re: shielding, I should offer more detail on the harness -- each has a
few twisted shielded pairs in there for Ethernet and RS-422, and these
interfaces are operating fine. The rest are all single-ended 26AWG
conventional PVC-insulated wire.

On Wed, Nov 25, 2015 at 11:01 AM, Chuck Corley
wrote:
It doesn't sound like the impedance of the traces and cables is being
controlled? Or signal termination is being used? That typically
leads to signal reflections, ringing, etc.

For JTAG, I have series termination at the drivers (3 at the test
equipment, 1 at the DUT for TDO) that tries to match to 50 ohm. I2C I
don't have any -- of course the bus has pull-up resistors on it, but
that is about it. I note that at the test equipment, TCK has a nasty
knee / signs of reflection, but at the DUT, the edge looks quite
clean.

Your outgoing signals are being split in the Y connector? That
changes whatever the impedance was at that point, possibly causing
reflections, etc.

It's a single connector on one end, and then it turns into two
circulars -- all the data signals are heading to the same circular
connector.

But the main problem is probably crosstalk. Your thoughts about the
return currents are on the right track, but that's part of the
problem, overall it sounds like you're probably having crosstalk
problems in the traces and cables. If there is no adjacent reference
return signal then there is nothing to set the cable/trace impedance
and act as a current return path, so your active signal edges will
crosstalk their way into adjacent signals like what you say you're
seeing. Maybe do a test to check which signals are adjacent in the
cable/board to see if they match the signals being corrupted, and
you'll probably confirm it's an adjacent signal crosstalk problem.

I've confirmed some aggressor / victim pairs, but additionally I've
confirmed that on piece of equipment, there's no crosstalk being
induced by the layouts. Firing up 1MHz TCK superimposes 1MHz noise on
SCL while active which is easily detectable -- it doesn't seem to be
the magnitude to cause problems, but it is definitely there.

The lack of reference return paths ("grounds") in the data harness
sounds like a problem. The number of grounds is situation/application
dependent. But for one example, on some slow applications like yours
where non-shielded cables are used I've sometimes had to alternate
every other line as ground/signal/ground/signal, etc. in order to set
some kind of a known signal impedance and current return path for the
signals traveling in the cable. This sounds more like what your data
cable might have needed.

It's late in the project (naturally), but I wonder if a hot-fix I
could do would be trying to twist each of my AC signals with a GND
wire in the harness length, and then tie all those GNDs together at
either end (to avoid having to add 6-8 pins from thin air).

In the example you're giving, was that a ribbon cable application? Or
did you actually twist certain cables together to ensure they
presented a known impedance (I assume that would be determined by the
turn ratio).

Thanks for all the help!
KD
Answered bymovax 4 years 10 months 24 days
Thanks for the replies all --

On Wed, Nov 25, 2015 at 12:05 PM, Lee Ritchey wrote:
Remember that "ground" doesn't have any meaning in the context of harnesses
like this. Transmission lines need partners such as shields on which their
return currents can flow. These shields also prevent cross talk. Probably
what will fix this problem.

This may be a more philosophical question -- do I treat these as
transmission lines despite the relatively 'slow' edge rates / clock
speeds I'm working with? I have no personal objection to this, but my
knowledge-base is such that I have a hard time explaining to people
why I'm treating a bus such as I2C (which is generally an
afterthought) as a transmission line. Certainly on a PCB, I don't
think much about it outside of routing it cleanly / minimizing plane
splits / jumps / etc.

Re: shielding, I should offer more detail on the harness -- each has a
few twisted shielded pairs in there for Ethernet and RS-422, and these
interfaces are operating fine. The rest are all single-ended 26AWG
conventional PVC-insulated wire.

On Wed, Nov 25, 2015 at 11:01 AM, Chuck Corley wrote:
It doesn't sound like the impedance of the traces and cables is being
controlled? Or signal termination is being used? That typically leads to
signal reflections, ringing, etc.

For JTAG, I have series termination at the drivers (3 at the test
equipment, 1 at the DUT for TDO) that tries to match to 50 ohm. I2C I
don't have any -- of course the bus has pull-up resistors on it, but
that is about it. I note that at the test equipment, TCK has a nasty
knee / signs of reflection, but at the DUT, the edge looks quite
clean.

Your outgoing signals are being split in the Y connector? That changes
whatever the impedance was at that point, possibly causing reflections, etc.

It's a single connector on one end, and then it turns into two
circulars -- all the data signals are heading to the same circular
connector.

But the main problem is probably crosstalk. Your thoughts about the return
currents are on the right track, but that's part of the problem, overall it
sounds like you're probably having crosstalk problems in the traces and
cables. If there is no adjacent reference return signal then there is
nothing to set the cable/trace impedance and act as a current return path, so
your active signal edges will crosstalk their way into adjacent signals like
what you say you're seeing. Maybe do a test to check which signals are
adjacent in the cable/board to see if they match the signals being corrupted,
and you'll probably confirm it's an adjacent signal crosstalk problem.

I've confirmed some aggressor / victim pairs, but additionally I've
confirmed that on piece of equipment, there's no crosstalk being
induced by the layouts. Firing up 1MHz TCK superimposes 1MHz noise on
SCL while active which is easily detectable -- it doesn't seem to be
the magnitude to cause problems, but it is definitely there.

The lack of reference return paths ("grounds") in the data harness sounds
like a problem. The number of grounds is situation/application dependent.
But for one example, on some slow applications like yours where non-shielded
cables are used I've sometimes had to alternate every other line as
ground/signal/ground/signal, etc. in order to set some kind of a known signal
impedance and current return path for the signals traveling in the cable.
This sounds more like what your data cable might have needed.

It's late in the project (naturally), but I wonder if a hot-fix I
could do would be trying to twist each of my AC signals with a GND
wire in the harness length, and then tie all those GNDs together at
either end (to avoid having to add 6-8 pins from thin air).

In the example you're giving, was that a ribbon cable application? Or
did you actually twist certain cables together to ensure they
presented a known impedance (I assume that would be determined by the
turn ratio).

Thanks for all the help!
KD
Answered byleeritchey 4 years 10 months 24 days
Remember that "ground" doesn't have any meaning in the context of harnesses 
like this. Transmission lines need partners such as shields on which their
return currents can flow. These shields also prevent cross talk. Probably
what will fix this problem.

-----
Answered bycorley 4 years 10 months 24 days
Hi KD,

Some of your thoughts show you're on the right track.

As I was reading your email it sounded like you have a number of issues,
I'll mention a few:

It doesn't sound like the impedance of the traces and cables is being
controlled? Or signal termination is being used? That typically leads
to signal reflections, ringing, etc.

Your outgoing signals are being split in the Y connector? That changes
whatever the impedance was at that point, possibly causing reflections,
etc.

But the main problem is probably crosstalk. Your thoughts about the
return currents are on the right track, but that's part of the problem,
overall it sounds like you're probably having crosstalk problems in the
traces and cables. If there is no adjacent reference return signal then
there is nothing to set the cable/trace impedance and act as a current
return path, so your active signal edges will crosstalk their way into
adjacent signals like what you say you're seeing. Maybe do a test to
check which signals are adjacent in the cable/board to see if they match
the signals being corrupted, and you'll probably confirm it's an
adjacent signal crosstalk problem.

The lack of reference return paths ("grounds") in the data harness
sounds like a problem. The number of grounds is situation/application
dependent. But for one example, on some slow applications like yours
where non-shielded cables are used I've sometimes had to alternate every
other line as ground/signal/ground/signal, etc. in order to set some
kind of a known signal impedance and current return path for the signals
traveling in the cable. This sounds more like what your data cable
might have needed.

Hope this helps!

Chuck


Chuck Corley




On 2015-11-25 10:28, Krunal Desai wrote:
HI all --

Hoping that list can shed some light on some wire harness related SI
questions at some very, very low speeds.

This list has done a good job teaching me about SI in general, and
especially the concept that while DC (i.e. power delivery) enjoys the
path of least resistance, the same is not true for AC signals (I think
rule of thumb says above 100kHz?).

We have a design where we have a 50-pin connector to our DUT on one
end. This goes to a Y-adapter which turns into 2x 32-pin MIL-STD
circular connectors, then a 6-8ft harness, and then our host / test
equipment box. Earlier this year, we decided to make one cable power,
and one cable data -- logical, right?

Recently though, we've observed severe SI issues when running two data
interfaces simultaneously (1MHz JTAG, and I2C) and this got me
thinking, and re-reading what we designed. Turns out that we were very
thorough in our power and data separation -- there are no grounds in
the data harness at all! This reminded me again of AC return currents
and their wanting to minimize loop area.

Here is my theory / gut feeling -- as the host box clocks out an edge
on lets say TCK, which is driven by a fairly "slow" driver (~15ns rise
time I think), at a frequency of 1MHz, it will leave the driver,
travel on a PCB trace, hop onto the harness, traverse the harness, hop
onto the DUT PCB and into the input device. Not to anthropomorphize
current too much, but at this point having made the long trip to the
DUT, he really wants to get home as fast as possible (and in as small
a loop area as possible). Unfortunately for him, the DC ground return
path is "far" away from the path he arrived on (the two cables kind of
flop around near each other), so he's going to take some path back in
the signal harness -- which could unfortunately be some output driver
that happens to be at '0', or some other data line. This isn't a
ribbon harness, so the conductors just float around in space
constrained only by braid. I think on my scope I can see odd /
increased noise when certain lines are low -- does that low impedance
path to GND encourage return current to flow on that line? If I idle
all I2C traffic, I get no errors on JTAG whatsoever, but when I2C
traffic begins to occur, my JTAG transaction quickly become corrupted.
This is the majority case; I've also observed the inverse behavior
where JTAG squashes I2C.

Am I on the right track here? Or should I be looking more for
reflections / impedance mismatches? This is not a fast interface
overall -- the edge rates aren't ultra-fast and I2C is an open-drain,
slow bus! (I have heard stories of people tuning the VOL strength of
their I2C devices before).

Additionally, I swear I remember reading somewhere an article (or
maybe it was on the list) for a good rule of thumb on how many return
conductors to provide for a given signal harness with n signal
conductors -- does anyone recall this?

Thanks! I'm hoping to work out / test this problem over Thanksgiving
-- it's a frustrating one, but those are also the ones that give you
the best feeling when you defeat them.

KD