What does an unpowered FPGA output look like on a TDR - pkg RLC only?

Hello SI-list!
Trying to figure out if an unpowered, area array FPGA output is connected to
PCB using TDR. I thought I might try to get an unmounted device to get a
baseline TDR signature for the unpowered FPGA output, but I don't have one yet.

Besides the package RLC parastitics, I'm thinking the unpowered device output
is likely going to look just like an open circuit. Do you agree? Was hoping
that maybe the ESD diodes would show up as a low impedance shunt to ground ,
but the TDR step is probably too small and too fast to trigger any ESD diodes
to conduct.

Does anybody have any other ideas?

Thanks !



John Nieznanski
Sr. Staff Engineer
Electronics Design, Assembly, Integration and Test
Geospatial Systems

Exelis Inc., a wholly owned subsidiary of Harris Corp.


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jnieznan 5 years 16 days

3 answers


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Answered bytom 5 years 16 days
John

You don't state if this IC pin is at the end of a trace or somewhere between
the source and the end. If the IC Pin is at the end of a trace and you can
probe it from the other end you will likely see a few hints that will help
you determine if the pin is connected or not. I assume the FPGA is in a BGA
package. Typically with a BGA package the solder pad/ball area will look
capacitive so you will see a dip in impedance at that point. As you move
further into the package you will see a transmission line usually near 50
Ohms. When the TDR signal finally gets to the silicon typically you will
see another capacitive region caused by C_comp, the capacitance associated
with the metal, etc. of the bond pad. After this, assuming there is no on
die termination, you will see an open. So the key in this case is the length
of the TDR response. If there is no IC at the end of the trace then you
will see a TDR response to an open of x.xx nsec. If the IC is present then
you will see a longer time x.xx nsec + Tpackage. So you don't need a IC
first measure the package to find its characteristics. What you need is a
board without that IC mounted. TDR the trace with no IC and compare it to
the board with the IC. If you don't have a bare board then you may be able
to determine if the IC is present based on what you see in the plot. And
remember if you can probe near the IC Pin on the board you can determine
where the end of the trace is. For example, a finger when placed on a trace
will add capacitance lowering the local impedance.

If you have the case where the IC Pin is not at the end of the trace you may
be able to see if there is a connection or not. An IC pin will have a set
of characteristics as described above. You can look at them as capacitors
at the end of a short transmission line. So if the trace to the IC connects
directly to the IC Pin then there will be a short stub causing a lowering of
impedance in that area. If the IC package and the trace both look like 50
Ohm transmission lines then you will see a short section of 25 Ohms with
small values of C at the beginning and end if the IC is present.


If the IC is connected to the main trace via a branch in the trace then you
will have a more complex analysis to do. But likely doable. If you have
multiple vias, ICs, connectors and other TDR discontinuities on the trace if
may be impossible to determine what is going on.

Oh, and remember if two items are spaced 1 nsec apart on a TDR plot they are
really 0.5nsec apart. With TDR the signal has to travel out and back so it
sees twice the amount of delay.

Tom Dagostino

971-279-5325
tom@xxxxxxxxxxxxxxxxx



-----
Answered byjeff.loyer.si 5 years 16 days
Hello John,
I've never experienced having the ESD diodes turn on when TDR'ing a device -
250mV is too small a voltage. You should be able to TDR a bare board
(solder samples often work well for this) and compare that to the board(s)
with the device populated. My guess is that the TDR trace after the PCB
would show:
1) parasitics of the FPGA connection - typically capacitive, compared to a
~50 ohm PCB trace,
2) package routing impedance - hard to predict whether they'll be above or
below your PCB trace, and it probably will have local perturbations,
3) C-pad. Parasitic capacitance of the device itself,
4) open.

Depending on your TDR risetime, you may not be able to discern all these
fine features, but you should definitely be able to see a change in the
propagation delay between the open of a bare and populated PCB.

Jeff Loyer
Signal Integrity Engineering

-----
Answered byal 5 years 16 days
Teraspeed Labs in Portland OR does all of our TDR testing for our Channel 
Modeling Platforms. I would call them. They do a great job for us.





Products for the Signal Integrity Practitioner



Alfred P. Neves
Chief Technologist



Office: 503-679-2429

www.wildrivertech.com
2015 Best In Design&Test Finalist








On Sep 4, 2015, at 7:39 AM, Nieznanski, John - Harris
wrote:

Hello SI-list!
Trying to figure out if an unpowered, area array FPGA output is connected to
PCB using TDR. I thought I might try to get an unmounted device to get a
baseline TDR signature for the unpowered FPGA output, but I don't have one
yet.

Besides the package RLC parastitics, I'm thinking the unpowered device output
is likely going to look just like an open circuit. Do you agree? Was hoping
that maybe the ESD diodes would show up as a low impedance shunt to ground ,
but the TDR step is probably too small and too fast to trigger any ESD diodes
to conduct.

Does anybody have any other ideas?

Thanks !



John Nieznanski
Sr. Staff Engineer
Electronics Design, Assembly, Integration and Test
Geospatial Systems

Exelis Inc., a wholly owned subsidiary of Harris Corp.


[https://integration.harris.com/assets/HARRIS_LOGOS/Email_logos/Harris_noR_email.jpg]
800 Lee Road
P.O. Box 60488
Rochester, NY 14606-0488
585 269 5740 Office
585 410 5214 Cell/Text
jnieznan@xxxxxxxxxx (Primary E-Mail)
john.nieznanski@xxxxxxxxxxxxx (Obsolete
E-Mail)
www.harris.com


________________________________

This e-mail and any files transmitted with it may be proprietary and are
intended solely for the use of the individual or entity to whom they are
addressed. If you have received this e-mail in error please notify the
sender. Please note that any views or opinions presented in this e-mail are
solely those of the author and do not necessarily represent those of Exelis
Inc. The recipient should check this e-mail and any attachments for the
presence of viruses. Exelis Inc. accepts no liability for any damage caused
by any virus transmitted by this e-mail.