10G SERDES issue

Hi All,

We have 10G SERDES channel between ASIC(MAC switch) and phy and there is no
issues if we initialize the system once and run the traffic .If we
reinitialize the system at particular interval ASIC throws an error and
the link is not up.


There is no issue till PMA SERDES of ASIC.


We measured reference clock and itâ??s clean and jitter, phase noise are
within the spec .We measured data eye(internal eye after EQ block) in
passing and failing condition and both looks good.


What could be a reason for this failure?

1. PLL loop bandwidth

2.Recovered clocks are not meeting the jitter tolerance?

3. Anything to do with Consecutive identical digits

4. Anything to do with phase aligner and sampling point

Regards
bala

balaseven 5 years 1 month 24 days

2 answers


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Answered byChris.Cotton 5 years 1 month 24 days
Check for extended idle periods before the error occurs. If the recovery PLL is 
trying to lock to data and not it's own reference and the data goes idle for an
extended period of time, the Rx PLL could be drifting and then fail to sample
correctly once real data starts up again.
Chris

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Answered byalan.hiltonnickel 5 years 1 month 24 days
It would be helpful if the ASIC generated an error code when it threw an 
error.

In addition to Chris' thoughts, I can add the following:

1. Is there a difference between the internal clock of the ASIC/Mac and
the channel. Sometimes crossing clock domains can cause unrecoverable
data errors.

2. You say the problem occurs when you reset the entire system at "a
particular interval" (not sure what that means). This suggests a large
power transient. You might want to check your power supply/PDN to see if
you have a dropout issue due to poor transient response.

Alan

On 8/25/2015 8:20 AM, bala wrote:
Hi All,

We have 10G SERDES channel between ASIC(MAC switch) and phy and there is no
issues if we initialize the system once and run the traffic .If we
reinitialize the system at particular interval ASIC throws an error and
the link is not up.


There is no issue till PMA SERDES of ASIC.


We measured reference clock and it’s clean and jitter, phase noise are
within the spec .We measured data eye(internal eye after EQ block) in
passing and failing condition and both looks good.


What could be a reason for this failure?

1. PLL loop bandwidth

2.Recovered clocks are not meeting the jitter tolerance?

3. Anything to do with Consecutive identical digits

4. Anything to do with phase aligner and sampling point

Regards
bala