Serdes Queries

Hi All,
I have some queries w.r.t. Serdes.

1. Ideally CDR transfer function -3dB corner freq(Low pass function) and
JTF(High pass function) -3dB corner freq should be same , but USB 3.0 spec
says former of 10Mhz while later of 5Mhz, why is it so?

2. What are the advantages of VML drivers over CML drivers? In recent times
Serdes drivers implement VML. So what benefit we get by using VML or what
drawbacks we have in CML so that VML drivers are preferred over them?

3.In PCIe, why data lanes are internally as well as externally terminated?
Why we need source as well as receiver termination?

4. In Rx Jitter tolerance test we sweep SJ from some low freq to 50/100Mhz
by adding SJ amplitudes at each step as per the spec and these amplitudes
are some percentage of UI. At some lower freq e.g 500Khz and 1Mhz or so ,
CDR is required to tolerate 200%UI or 100%UI or some value as per the spec.
So I am wondering if we are adding this huge amount of jitter , then how
CDR is able to track this and then sampling happens with
the recovered clock from CDR?

Thanks and Regards,
Bhavani


bhavanipadhi 5 years 3 months 19 days

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Answered bybhavanipadhi 5 years 3 months 19 days
Hi All,
I have some queries w.r.t. Serdes.

1. Ideally CDR transfer function -3dB corner freq(Low pass function) and
JTF(High pass function) -3dB corner freq should be same , but USB 3.0 spec
says former of 10Mhz while later of 5Mhz, why is it so?

2. What are the advantages of VML drivers over CML drivers? In recent times
Serdes drivers implement VML. So what benefit we get by using VML or what
drawbacks we have in CML so that VML drivers are preferred over them?

3.In PCIe, why data lanes are internally as well as externally terminated?
Why we need source as well as receiver termination?

4. In Rx Jitter tolerance test we sweep SJ from some low freq to 50/100Mhz
by adding SJ amplitudes at each step as per the spec and these amplitudes
are some percentage of UI. At some lower freq e.g 500Khz and 1Mhz or so ,
CDR is required to tolerate 200%UI or 100%UI or some value as per the spec.
So I am wondering if we are adding this huge amount of jitter , then how
CDR is able to track this and then sampling happens with
the recovered clock from CDR?

Thanks and Regards,
Bhavani


Answered bybhavanipadhi 5 years 3 months 19 days
Hi All,
I have some queries w.r.t. Serdes.

1. Ideally CDR transfer function -3dB corner freq(Low pass function) and
JTF(High pass function) -3dB corner freq should be same , but USB 3.0 spec
says former of 10Mhz while later of 5Mhz, why is it so?

2. What are the advantages of VML drivers over CML drivers? In recent times
Serdes drivers implement VML. So what benefit we get by using VML or what
drawbacks we have in CML so that VML drivers are preferred over them?

3.In PCIe, why data lanes are internally as well as externally terminated?
Why we need source as well as receiver termination?

4. In Rx Jitter tolerance test we sweep SJ from some low freq to 50/100Mhz
by adding SJ amplitudes at each step as per the spec and these amplitudes
are some percentage of UI. At some lower freq e.g 500Khz and 1Mhz or so ,
CDR is required to tolerate 200%UI or 100%UI or some value as per the spec.
So I am wondering if we are adding this huge amount of jitter , then how
CDR is able to track this and then sampling happens with
the recovered clock from CDR?

Thanks and Regards,
Bhavani