On the use of "dots" for copper balance

Hello all,Has anyone analyzed the impact of the addition of copper dots (used to balance the copper etch on a pwb) onhigh speed pwbs?  The proposal is NOT to ground these dots.  I can see from an SI standpoint that these present acapacitive load that could add unwanted dips in the waveform but I cannot imagine an EMI issue..am I wrong?Are there any presentations I can look at? (A Google search for brought up some interesting results!)??Best RegardsCharles GrassoCompliance EngineerEchostar Communications(w) 303-706-5467(c) 303-204-2974(t) 3032042974@xxxxxxxxx(e) charles.grasso@xxxxxxxxxxxx(e2) chasgrasso@xxxxxxxxx
Charles.Grasso 5 years 10 months 19 days

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Answered byferhatyaldiz 5 years 10 months 16 days
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Answered byferhatyaldiz 5 years 10 months 16 days
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Answered byCharles.Grasso 5 years 10 months 18 days
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Answered bybretadair 5 years 10 months 18 days
Hello Charles,Upon receiving respective technical questions from board fabrication housesof gerber files, they indubitably include the copper thieving request. Mypersonal schedule pressures have dictated a time frame which has neverallowed an analysis to respond to this request. Therefore my response hasbeen essentially a regurgitation from our SI engineers, and that is, noimpact. However, I felt uneasy to just accept these inputs in both the SIand EMI domains as I believe copper thieving dots DO impact expectedperformance.NOTE - I am a PCB designer. I do not postulate that I have empirical norscholastic knowledge on this subject. What I DO have is historicalexperience of advancing technologies. With that, I am resistant to statethat a concern be ruled out as inconsequential. Although, I must admit thatI have abided by this practice to date.I am taking the liberty of restating your question into the questions Ihave been asking:Q1 - What is the value for the customer if board fabricators to add copperthieving? Bellow are typical responses they may tout:A1a - Reduce the amount of copper to be etched away = better time andsolution (material) savingsA1b - Greater trace geometry consistency = better yieldA1c - Greater stability during lamination press = better yieldA1x - Please add any/all comments you have heardAssuming the above comments are true, if we conform to their requests, haveanyone seen a benefit or are we just increasing their margins at thepotential risk of performance?Q2 - If copper thieving is added to a design, then is there potential forthe copper thieving to impact the expected performance?This is what I alluded to in regards to SI and EMI. A shoot from the hipresponse may state "well as long as your X mils/mm or X h away, you will befine". I accept this response, but I believe the distance needs to beclearly identified. Meaning the spacing should be based on the instance.Voltage potential may allude to spacing by cleanliness, creepage andclearance; frequency may allude to spacing based on acceptable loss, etc.As for the EMI aspect, I have an unsupported belief that if copper thievinggeometries are stacked in the Z dimension (Layer 1 and Layer 2) that as aconductor carrying a high frequency signal below said stacked thievinggeometries (Layer 3), that the signal will couple in the Z dimension,thereby radiating out through the surface layer. I acknowledge that saidstackup is rare, but I have designed boards as such. However, if Layer 2 isa plane, then I also suspect that a Layer 3 trace will induce fields onLayer 2 on the surface adjacent to Layer 3. Which will in turn inducefields on Layer 2 on the surface adjacent to Layer 1. Thereby, emittingfields beyond the board surface. I would prefer to know what this emissionfield strength is and what is acceptable.Going back to the question, is this an impact to the expected performance?Yes I know, this "should be" defined by whatever the system specificationcalls out, but such requirements are at best only calling out someregulatory certification.Q3 - If there is a potential for the copper thieving to impact the expectedperformance, then how can PCB designers minimize the impact?Knowing such information could then incorporate Faraday cages such assurface planes, shield boxes, etc. as needed.Assuming these questions are answered in a quantitative manner, we couldthen assess the potential value (savings) versus the potential risk ofperformance. My shoot from the hip is leaning more towards not adding thethieving, but I will hold making the switch until I have better input.Regards,BretOn Mon, Nov 3, 2014 at 3:20 PM, Loyer, Jeff  wrote:> I don't think thieving is just done for plating uniformity.  For years,> I've seen vendors put thieving on inner layers and I was told that was for> prepreg thickness consistency and etching uniformity.  I'm also told (by> PCB experts) that many (most?) outer layers are now being done with "panel> plating" (vs. "pattern plating" that you're describing), and that nullifies> the benefit of thieving if it was only for plating uniformity.  Of course,> this is for my domain, which is server boards.  I don't know what processes> are commonly used for cell phones, etc.>> To answer the original question, I agree with Lee that the metal is kept> far enough away from any signals to preclude issues (in theory, anyway).> Be especially careful if you have buried microstrip, or a dual stripline> design (as Lee said).>> FYI (some terminology):> "panel plate": plate the entire outer layers and then etch the> geometries.  Can't be used for the finer (<4mil) geometries, but I'm told> it's being used very often now.  Cross-sectioning many boards indicates it> is usually being used (as evidenced by the microstrip profile - curved> walls, signs of undercutting, etc.).  Thieving wouldn't make any difference> to trace plating thickness, it would only affect the etching.> "pattern plate": only plate the desired geometries.  This was the> conventional technique, and thieving affected plating thickness> significantly. Cross-sectioning of these boards shows the conventional> "rectangle on a trapezoid" profile.>> As always, I welcome others' information or data, even if it contradicts> my current understanding.> Jeff Loyer>>> -----
Answered byjeff.loyer 5 years 10 months 18 days
I don't think thieving is just done for plating uniformity.  For years, I've seen vendors put thieving on inner layers and I was told that was for prepreg thickness consistency and etching uniformity.  I'm also told (by PCB experts) that many (most?) outer layers are now being done with "panel plating" (vs. "pattern plating" that you're describing), and that nullifies the benefit of thieving if it was only for plating uniformity.  Of course, this is for my domain, which is server boards.  I don't know what processes are commonly used for cell phones, etc.To answer the original question, I agree with Lee that the metal is kept far enough away from any signals to preclude issues (in theory, anyway).  Be especially careful if you have buried microstrip, or a dual stripline design (as Lee said).FYI (some terminology):"panel plate": plate the entire outer layers and then etch the geometries.  Can't be used for the finer (<4mil) geometries, but I'm told it's being used very often now.  Cross-sectioning many boards indicates it is usually being used (as evidenced by the microstrip profile - curved walls, signs of undercutting, etc.).  Thieving wouldn't make any difference to trace plating thickness, it would only affect the etching."pattern plate": only plate the desired geometries.  This was the conventional technique, and thieving affected plating thickness significantly. Cross-sectioning of these boards shows the conventional "rectangle on a trapezoid" profile.As always, I welcome others' information or data, even if it contradicts my current understanding. Jeff Loyer-----
Answered byleeritchey 5 years 10 months 19 days
Yes, this is only done on the outside layers of a PCB to even out the copper distribution so plating in the holes is uniform.  The dots are not connected to anything after etching has been done.  As long as they are not on top of traces in layer 2 or layer n-1 they do no harm.-----
Answered byaaditya.kandibanda 5 years 10 months 19 days
Hi,Is it  "Copper Thieving?"Isn't it applied on only top/bottom layer?ThanksAadityaOn Mon, Nov 3, 2014 at 10:00 AM, Grasso, Charles  wrote:> Hello all,> Has anyone analyzed the impact of the addition of copper dots (used to> balance the copper etch on a pwb) on> high speed pwbs?  The proposal is NOT to ground these dots.  I can see> from an SI standpoint that these present a> capacitive load that could add unwanted dips in the waveform but I cannot> imagine an EMI issue..am I wrong?>> Are there any presentations I can look at? (A Google search for brought up> some interesting results!)??>> Best Regards> Charles Grasso> Compliance Engineer> Echostar Communications> (w) 303-706-5467> (c) 303-204-2974> (t) 3032042974@xxxxxxxxx> (e) charles.grasso@xxxxxxxxxxxx> (e2) chasgrasso@xxxxxxxxx>>>