DDR2 problem

Having some issues with a 225MHz DDR2 implementation at high temperature.I am wondering if the problem might be power plane related. Doing a S21 analysis shows there is a bit of an impedance hole around 260MHz. Its magnitude or frequency doesn't change with temperature, but unsurprisingly does with applied voltage (1.8V). It's Q is not particularly high.The issue showed up when we were forced to start using a die shrunk part. (Yes, I know. That probably gives some clues). The original part worked over 100 degreesC with no problem at 225MHz. The new part starts failing at 60C. It doesn't appear to be a refresh problem. The new part is supposed to work to 500MHz. But the interesting thing is that if the clock rate is dropped to 200MHz everything works fine. We did have some issues with the original implementation at 250MHz at any temperature, hence why we were operating at 225MHz.The power plane is not much bigger than a postage stamp. And the ground planes for it are 0.12mm away. All data, address and control lines are length matched. There are 8 bypass caps, all 100n. There is only one SDRAM and a Freescale processor. Interconnects are all on internal layers. Line lengths are about 20mm. There are no series termination resistors as the layout is rather compact.Regards,Bryan Ackerly.
bryan 6 years 1 month

3 answers


The best answer


You can select the best answer for current question!
Answered byHermann.Ruckerbauer 6 years 29 days
Hello,I have seen one freescale controller (don't remember which one it was) failing with new memory devices because an internal weakness of the VrefDecoupling.There was some internal coupling to Vref and due to stronger driversthis caused the reads to fail.Not easy to detect, as there is no real external indication whenmeasuring signal quality.A vref margin test showed the basic weakness, even with the original DRAMs.=> thats the reason why I always recommend not just to do some softwarememory tests at different temps, but also do a Compliance measurementand a Vref margin test on new designs ..There was a freescale application note showing a special externaldecoupling on VREF to overcome the issue..This one was not easy to find .. just when we convinced freescale thatwe there is some internal controller issue (as we have shown that thereis no external signalin issee)  they pulled this out of the hat ..Maybe you are running in the same issue ..HermanEKH - EyeKnowHowHermann Ruckerbauerwww.EyeKnowHow.deHermann.Ruckerbauer@xxxxxxxxxxxxxItzlinger Strasse 21a94469 DeggendorfTel.:   +49 (0)991 / 29 69 29 05Mobile: +49 (0)176  / 787 787 77Fax:    +49 (0)3212 / 121 9008Am 02.11.2014 um 09:37 schrieb Ferhat Yaldiz:> Bryan,> Generally failure arises from timing or quality with cold or hot> temperatures because of having short edge rates of new die.>   * You can reduce buffer strength if it is possible and try quickly from> bootloader.>   * You must simulate your DDR bus including timing-quality-crosstalk>     with all PVT corners and IBIS file of new die.>   * It could better if power effects are included simulations like SSN.> Best Regards,> Ferhat Yaldiz> On Sat, Nov 1, 2014 at 5:10 PM, Scott McMorrow  wrote:>>> brian>> your last line says everything.  DDR2 is a reflected wave signalling system>> with low impedance non-matched drivers.  What you have is a quarter-wave>> resonance that is established between the low impedance drivers and the>> high impedance receiver inputs. I'm guessing that if we analyzed the full>> path from die to die that we would find a resonance causing ringing that>> rings back into the threshold region.  Your new die shrunk part has faster>> edge rates that make the ringing higher amplitude.>>>> Your solution is to add series resistors,as was designed for the bus.>>>> regards,>>>> Scott>>>>>> Scott McMorrow>> Teraspeed® Consulting - A Division of Samtec>> 16 Stormy Brook Rd>> Falmouth, ME 04105>> (401) 284-1827 Business>> http://www.teraspeed.com>>>> On Fri, Oct 31, 2014 at 8:13 PM, Bryan Ackerly >> wrote:>>>>> Having some issues with a 225MHz DDR2 implementation at high temperature.>>> I am wondering if the problem might be power plane related. Doing a S21>>> analysis shows there is a bit of an impedance hole around 260MHz. Its>>> magnitude or frequency doesn't change with temperature, but>> unsurprisingly>>> does with applied voltage (1.8V). It's Q is not particularly high.>>>>>> The issue showed up when we were forced to start using a die shrunk part.>>> (Yes, I know. That probably gives some clues). The original part worked>>> over 100 degreesC with no problem at 225MHz. The new part starts failing>> at>>> 60C. It doesn't appear to be a refresh problem. The new part is supposed>> to>>> work to 500MHz. But the interesting thing is that if the clock rate is>>> dropped to 200MHz everything works fine. We did have some issues with the>>> original implementation at 250MHz at any temperature, hence why we were>>> operating at 225MHz.>>>>>> The power plane is not much bigger than a postage stamp. And the ground>>> planes for it are 0.12mm away. All data, address and control lines are>>> length matched. There are 8 bypass caps, all 100n. There is only one>> SDRAM>>> and a Freescale processor. Interconnects are all on internal layers. Line>>> lengths are about 20mm. There are no series termination resistors as the>>> layout is rather compact.>>>>>> Regards,>>> Bryan Ackerly.>>> 
Answered byferhatyaldiz 6 years 29 days
Bryan,Generally failure arises from timing or quality with cold or hottemperatures because of having short edge rates of new die.  * You can reduce buffer strength if it is possible and try quickly frombootloader.  * You must simulate your DDR bus including timing-quality-crosstalk    with all PVT corners and IBIS file of new die.  * It could better if power effects are included simulations like SSN.Best Regards,Ferhat YaldizOn Sat, Nov 1, 2014 at 5:10 PM, Scott McMorrow  wrote:> brian> your last line says everything.  DDR2 is a reflected wave signalling system> with low impedance non-matched drivers.  What you have is a quarter-wave> resonance that is established between the low impedance drivers and the> high impedance receiver inputs. I'm guessing that if we analyzed the full> path from die to die that we would find a resonance causing ringing that> rings back into the threshold region.  Your new die shrunk part has faster> edge rates that make the ringing higher amplitude.>> Your solution is to add series resistors,as was designed for the bus.>> regards,>> Scott>>> Scott McMorrow> Teraspeed® Consulting - A Division of Samtec> 16 Stormy Brook Rd> Falmouth, ME 04105> (401) 284-1827 Business> http://www.teraspeed.com>> On Fri, Oct 31, 2014 at 8:13 PM, Bryan Ackerly > wrote:>> > Having some issues with a 225MHz DDR2 implementation at high temperature.> > I am wondering if the problem might be power plane related. Doing a S21> > analysis shows there is a bit of an impedance hole around 260MHz. Its> > magnitude or frequency doesn't change with temperature, but> unsurprisingly> > does with applied voltage (1.8V). It's Q is not particularly high.> >> > The issue showed up when we were forced to start using a die shrunk part.> > (Yes, I know. That probably gives some clues). The original part worked> > over 100 degreesC with no problem at 225MHz. The new part starts failing> at> > 60C. It doesn't appear to be a refresh problem. The new part is supposed> to> > work to 500MHz. But the interesting thing is that if the clock rate is> > dropped to 200MHz everything works fine. We did have some issues with the> > original implementation at 250MHz at any temperature, hence why we were> > operating at 225MHz.> >> > The power plane is not much bigger than a postage stamp. And the ground> > planes for it are 0.12mm away. All data, address and control lines are> > length matched. There are 8 bypass caps, all 100n. There is only one> SDRAM> > and a Freescale processor. Interconnects are all on internal layers. Line> > lengths are about 20mm. There are no series termination resistors as the> > layout is rather compact.> >> > Regards,> > Bryan Ackerly.> > 
Answered byscott 6 years 1 month
brianyour last line says everything.  DDR2 is a reflected wave signalling systemwith low impedance non-matched drivers.  What you have is a quarter-waveresonance that is established between the low impedance drivers and thehigh impedance receiver inputs. I'm guessing that if we analyzed the fullpath from die to die that we would find a resonance causing ringing thatrings back into the threshold region.  Your new die shrunk part has fasteredge rates that make the ringing higher amplitude.Your solution is to add series resistors,as was designed for the bus.regards,ScottScott McMorrowTeraspeed® Consulting - A Division of Samtec16 Stormy Brook RdFalmouth, ME 04105(401) 284-1827 Businesshttp://www.teraspeed.comOn Fri, Oct 31, 2014 at 8:13 PM, Bryan Ackerly  wrote:> Having some issues with a 225MHz DDR2 implementation at high temperature.> I am wondering if the problem might be power plane related. Doing a S21> analysis shows there is a bit of an impedance hole around 260MHz. Its> magnitude or frequency doesn't change with temperature, but unsurprisingly> does with applied voltage (1.8V). It's Q is not particularly high.>> The issue showed up when we were forced to start using a die shrunk part.> (Yes, I know. That probably gives some clues). The original part worked> over 100 degreesC with no problem at 225MHz. The new part starts failing at> 60C. It doesn't appear to be a refresh problem. The new part is supposed to> work to 500MHz. But the interesting thing is that if the clock rate is> dropped to 200MHz everything works fine. We did have some issues with the> original implementation at 250MHz at any temperature, hence why we were> operating at 225MHz.>> The power plane is not much bigger than a postage stamp. And the ground> planes for it are 0.12mm away. All data, address and control lines are> length matched. There are 8 bypass caps, all 100n. There is only one SDRAM> and a Freescale processor. Interconnects are all on internal layers. Line> lengths are about 20mm. There are no series termination resistors as the> layout is rather compact.>> Regards,> Bryan Ackerly.>