what's the minimum trace distance from the pcb ed......


Hi experts,What's the acceptable distance from the pcb edges for high-speed digital traces from EMI ......

asked by ihirshtal lastest answer by Old_School

5 years 3 months 2 days

0

votes

2

answers
3319 views

VRM hands-on workshop


YïëzÚò?x-¢®è§µê޲اj§vÏè?+?Èh¥úºÇ¢{azg?²êÞ?éíþjzX§?ÿÿ²)®?«b¢v§v?m?h³jب??ÕDÏìÿÿÈ~Ø^­æ«{^ÿÛH§µê......

asked by Steve

5 years 3 months 2 days

0

votes

0

answers
1727 views

Re: si-list Digest V16 #31


YèZ½é趷?z+Þvf§Ê·¬¦?ìzȧv'¶)à?{^­ë-?v?DÉ?jË«zg§·ù¨uéb?§vȦºV­??ð¢¹,??ÿÿòÁêÞqè¯{^ÿÛJÞ?+-­«b¢zު笶......

asked by steve

5 years 3 months 2 days

0

votes

0

answers
2150 views

Power Supply Noise injected Jitter impact on SERD......


Hi All,In my design I have high speed interfaces like DDR4 and PCIe 3.0 interfaceoperating at their ......

asked by rameshp3note lastest answer by carsona

5 years 3 months 5 days

0

votes

1

answers
2740 views

Job Opening at Qualcomm: Signal Integrity Enginee......


Hello,Qualcomm Package Electrical Group has a Job opening in San Diego, CA for a qualified Candidate......

asked by moshiulh

5 years 3 months 5 days

0

votes

0

answers
2805 views

DSR-3241 soldermask Dk and Df?


Hello,I was wondering if anyone happens to know the dielectric constant and losstangent for DSR-3241......

asked by fisayo.adepetun lastest answer by fisayo.adepetun

5 years 3 months 6 days

0

votes

2

answers
3326 views

Re: si-list Digest V16 #25


How many of you would be interested in a VRM workshop in northern CA? We are planning one know. It's......

asked by ssandler1

5 years 3 months 6 days

0

votes

0

answers
1633 views

Re: si-list Digest V16 #24


A few things to recognize, folksFirst, ANYONE can build an averaged model which is state space plane......

asked by Steve lastest answer by Steve

5 years 3 months 6 days

0

votes

3

answers
3676 views

Fwd: VRM bode plot transformation into output imp


---------- Forwarded message ----------From: Don Pakbaz Date: Wed, Jan 13, 2016 at 8:43 AMSubject: V......

asked by don.pakbaz

5 years 3 months 6 days

0

votes

0

answers
2682 views

VRM bode plot transformation into output imp prof......


Hi,This post is about theories on VRM modelling.For power integrity analysis ideally we should combi......

asked by buenoshun lastest answer by jun.zhou

5 years 3 months 7 days

0

votes

13

answers
4910 views

Re: two new posts on PDN noise


FYI:two new posts were added to the Quietpower columns onhttp://www.electrical-integrity.com/- How t......

asked by istvan.novak lastest answer by emcesd

5 years 3 months 8 days

0

votes

1

answers
2285 views

Radio show Jan. 15: Ransom Stephens on PAM4


Just in time for DesignCon, EE Times will broadcast a radio show featuring Ransom Stephens.PAM4 Sign......

asked by martin.rowe lastest answer by ransom

5 years 3 months 11 days

0

votes

1

answers
2837 views

There are not 2, there are six ... How to specify......


Jeff,If your design is limited to simple through hole vias, then two hole sizes are required - finis......

asked by wkatz

5 years 3 months 13 days

0

votes

0

answers
2476 views

Upcoming Webinar on Trace Current/Temperature rel......


I will be giving a webinar hosted by C-Therm Technologies entitled "Thermal Conductivity of Printed ......

asked by dbrooks9

5 years 3 months 14 days

0

votes

0

answers
2058 views

upcoming design and troubleshooting class/seminar


Hi Everyone,It's that time of year for my February 22nd-24th (Monday through Wednesday)design and tr......

EMC

asked by doug

5 years 3 months 16 days

0

votes

0

answers
2024 views

Generic vs. specific stackups for PCB designers


I have a question targeted at the design and signal integrity engineersâ??perspective, not PCB fabri......

asked by jeff.loyer lastest answer by buenoshun

5 years 3 months 19 days

0

votes

2

answers
4187 views

Influence of 8b10 encoder to eye diagram


Hi experts,In simulation of SAS-3 12Gbps by IBIS-AMI model obtained from vendors, Iaccidently compar......

asked by zhangjun5960 lastest answer by vladimir_dmitriev-zdorov

5 years 3 months 20 days

0

votes

11

answers
4787 views

How to specify via hole sizes


One thing that has bothered me forever is the ambiguity in specifying viahole sizes. To my mind, the......

asked by jeff.loyer lastest answer by buenoshun

5 years 3 months 21 days

0

votes

6

answers
4246 views

Glass Weave effects and Cross sectioning


Hi experts,I've been reading much on glass weave effects and its contribution on skew.If I encounter......

asked by bbakshan lastest answer by istvan.novak

5 years 3 months 22 days

0

votes

49

answers
5459 views

ground recessing


Hi experts,I approach a case about ground recessing. For eight PCIE lanes, the sixteenAC caps are in......

asked by zhangjun5960 lastest answer by leeritchey

5 years 4 months 26 days

0

votes

16

answers
4541 views
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