what's the minimum trace distance from the pcb ed......
Hi experts,What's the acceptable distance from the pcb edges for high-speed digital traces from EMI ......
asked by ihirshtal lastest answer by Old_School
0
votes
VRM hands-on workshop
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asked by Steve
0
votes0
answers
Re: si-list Digest V16 #31
YèZ½é趷?z+Þvf§Ê·¬¦?ìzȧv'¶)à?{^ë-?v?DÉ?jË«zg§·ù¨uéb?§vȦºV??ð¢¹,??ÿÿò ÁêÞqè¯{^ÿÛJÞ?+-«b¢zު笶......
asked by steve
0
votes0
answers
Power Supply Noise injected Jitter impact on SERD......
Hi All,In my design I have high speed interfaces like DDR4 and PCIe 3.0 interfaceoperating at their ......
asked by rameshp3note lastest answer by carsona
0
votes1
answers
Job Opening at Qualcomm: Signal Integrity Enginee......
Hello,Qualcomm Package Electrical Group has a Job opening in San Diego, CA for a qualified Candidate......
asked by moshiulh
0
votes0
answers
DSR-3241 soldermask Dk and Df?
Hello,I was wondering if anyone happens to know the dielectric constant and losstangent for DSR-3241......
asked by fisayo.adepetun lastest answer by fisayo.adepetun
0
votes2
answers
Re: si-list Digest V16 #25
How many of you would be interested in a VRM workshop in northern CA? We are planning one know. It's......
asked by ssandler1
0
votes0
answers
Re: si-list Digest V16 #24
A few things to recognize, folksFirst, ANYONE can build an averaged model which is state space plane......
0
votes3
answers
Fwd: VRM bode plot transformation into output imp
---------- Forwarded message ----------From: Don Pakbaz Date: Wed, Jan 13, 2016 at 8:43 AMSubject: V......
asked by don.pakbaz
0
votes0
answers
VRM bode plot transformation into output imp prof......
Hi,This post is about theories on VRM modelling.For power integrity analysis ideally we should combi......
0
votes13
answers
Re: two new posts on PDN noise
FYI:two new posts were added to the Quietpower columns onhttp://www.electrical-integrity.com/- How t......
asked by istvan.novak lastest answer by emcesd
0
votes1
answers
Radio show Jan. 15: Ransom Stephens on PAM4
Just in time for DesignCon, EE Times will broadcast a radio show featuring Ransom Stephens.PAM4 Sign......
asked by martin.rowe lastest answer by ransom
0
votes1
answers
There are not 2, there are six ... How to specify......
Jeff,If your design is limited to simple through hole vias, then two hole sizes are required - finis......
asked by wkatz
0
votes0
answers
Upcoming Webinar on Trace Current/Temperature rel......
I will be giving a webinar hosted by C-Therm Technologies entitled "Thermal Conductivity of Printed ......
asked by dbrooks9
0
votes0
answers
upcoming design and troubleshooting class/seminar
Hi Everyone,It's that time of year for my February 22nd-24th (Monday through Wednesday)design and tr......
asked by doug
0
votes0
answers
Generic vs. specific stackups for PCB designers
I have a question targeted at the design and signal integrity engineersâ??perspective, not PCB fabri......
asked by jeff.loyer lastest answer by buenoshun
0
votes2
answers
Influence of 8b10 encoder to eye diagram
Hi experts,In simulation of SAS-3 12Gbps by IBIS-AMI model obtained from vendors, Iaccidently compar......
asked by zhangjun5960 lastest answer by vladimir_dmitriev-zdorov
0
votes11
answers
How to specify via hole sizes
One thing that has bothered me forever is the ambiguity in specifying viahole sizes. To my mind, the......
asked by jeff.loyer lastest answer by buenoshun
0
votes6
answers
Glass Weave effects and Cross sectioning
Hi experts,I've been reading much on glass weave effects and its contribution on skew.If I encounter......
asked by bbakshan lastest answer by istvan.novak
0
votes49
answers
ground recessing
Hi experts,I approach a case about ground recessing. For eight PCIE lanes, the sixteenAC caps are in......
asked by zhangjun5960 lastest answer by leeritchey
2
answers